NVMe Self-Study Bank: Integrated validation and evidence correlation
NVMe · Q1–328
Q297–Q320
Integrated validation and evidence correlation
Apply prior mechanisms to apparent contradictions, matching identity and time before judging evidence.
Each question is followed by its explanation. Start with the volume overview, then follow the field interpretations, comparisons or processes. Essential conditions and the normal path are visible from the start. All numerical examples are hypothetical. Status is written SCT/SC; h indicates hexadecimal.
- SCT
- Status Code Type
A reproducible evidence path
State the requirement before collecting evidence; volume is not completeness.
| Stage | Preserve | Avoid |
|---|---|---|
| Preconditions | Support, scope, configuration, state | Support means all requests are legal |
| Operation | Request, selectors, time | Reconstructed rather than original evidence |
| Results | Completion, logs, events | Acceptance equals operation completion |
| Persistence | Reset type and state changes | All resets have identical effects |
Worked interpretation: Successful initiation with progress is normal; confirmed final completion with persistent same-scope in-progress data needs investigation.
Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.13–5.2.13.1.1 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding)
Review the terminology when needed
- Controller / namespace
- A controller receives commands and manages access. A namespace is a logical storage space that commands can address. An NVM subsystem contains controllers and nonvolatile storage resources.
- SQ / CQ / SQE / CQE
- Submission and Completion Queues carry command entries (SQEs) and completion entries (CQEs). QID identifies a queue, CID distinguishes outstanding commands in one SQ, and NSID identifies a namespace.
- Register / Identify / Feature / Log
- A register exposes control or state. Identify queries capabilities and attributes; features query or configure operation; log pages report specific state or records. FID, LID, CNS and CSI select features, logs, Identify structures and command sets.
- index / offset / zero-based
- An index selects an entry, usually starting at 0; an offset measures distance from an origin in specified units. A zero-based count encodes count−1, but not every zero-valued field is a count. A Dword is 4 bytes; a byte is 8 bits.
- Scope / reset / retention
- Scope names the affected objects; retention means preserving state. Controller Reset (clearing CC.EN) is one form of Controller Level Reset, or CLR. Different CLR triggers can retain different registers.
Questions in this volume
- Q297 · Where do you start when an advertised command fails?
- Q298 · Does success of an unadvertised command prove compliance?
- Q299 · How is a successful Set with different readback or behavior investigated?
- Q300 · Why might an AER completion have no matching visible log information?
- Q301 · Does every failed CQE require a new error entry?
- Q302 · When do differing CQE, Error Information and PEL records conflict?
- Q303 · How are unexpected feature retention or lost saved values assessed?
- Q304 · How are namespace changes reconciled across Identify, lists and AER?
- Q305 · How are unchanged firmware revision or slot fields assessed after activation?
- Q306 · Is an in-progress log after sanitize command success an error?
- Q307 · How is a missing result after self-test investigated?
- Q308 · How are unexpected unsafe-shutdown counts assessed?
- Q309 · Which settings explain a warning change without an AER?
- Q310 · How is apparent PEL event-order mismatch investigated?
- Q311 · What evidence remains when CFS is set with little diagnostic information?
- Q312 · How are two observed completions after Abort classified?
- Q313 · What is wrong with queue-memory access after completed deletion?
- Q314 · How should a CQE from before reset be handled?
- Q315 · When can command success after detach be reasonable?
- Q316 · How is apparent Lockdown bypass investigated?
- Q317 · How is excessive power-state recovery latency measured correctly?
- Q318 · How are three reset types compared for one feature?
- Q319 · How is an operation’s real scope established?
- Q320 · How are the interfaces combined into one conformance investigation?
Q297 Where do you start when an advertised command fails?
Follow the explanation
Distinguish command support from legality and executability of this request.
1. Preserve the evidence first
Match controller, command set, namespace and time before comparing support.
Preserve Identify support, CSUPP and CSI/UUID selectors.
- CSI
- Command Set Identifier
If supported Format returns Invalid Format, compare its LBAF with the namespace’s formats.
2. Work through the possible causes
First inspect SCT/SC rather than an application’s generic failure label.
- SCT
- Status Code Type
Decode the CQE, then validate selectors, namespace state, protection and active-operation restrictions.
- CQE
- Completion Queue Entry
3. Connect observations to specification conditions
Rejecting an unsupported LBA format can be consistent with supporting Format.
- LBA
- Logical Block Address
Invalid Opcode with all prerequisites met warrants support-consistency investigation, not an automatic conclusion from any failure.
Use a contemporaneous valid control differing in one relevant condition.
Sources: Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.13.1.6 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.13.1.6 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q298 Does success of an unadvertised command prove compliance?
Follow the explanation
Success does not correct an inaccurate capability declaration.
1. Preserve the evidence first
Establish applicability to controller type, command set and query revision.
Compare the relevant discovery interface rather than unrelated capability bits.
CSUPP0 and successful effective execution of that opcode under the same CSI require investigation.
- CSI
- Command Set Identifier
2. Work through the possible causes
First compare discovery and execution selectors.
Exclude stale snapshots, activation, opcode-category confusion and reserved-field misinterpretation.
3. Connect observations to specification conditions
Capability, completion and observable effects must agree.
Require rejection only where the specification defines unsupported behavior; inapplicable zero fields do not universally prohibit commands.
Preserve contradictory evidence and cite the exact declaration rule.
Sources: Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.13.1.6 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.13.1.6 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q299 How is a successful Set with different readback or behavior investigated?
Follow the explanation
Separate acceptance, current value, saved value and actual effect.
1. Preserve the evidence first
Feature scope determines the target that Get must match.
Check supported capabilities and whether the feature may adjust requested values.
KATO may round up to KAS granularity, so a larger readback is not necessarily wrong.
2. Work through the possible causes
First rule out reading a different kind of value before concluding that the controller failed to apply a setting.
- Preserve the Set request and successful completion
Record FID, SV, NSID, other selectors and the payload.
- Read Current with SEL=0 on the same target
Default, Saved or another namespace’s value does not directly verify this current setting.
- Check allowed adjustment, then observe behavior
A permitted adjusted value with matching behavior can be a valid successful result.
- To test saving, separately inspect Saved and the specified reset
Persistence is a separate test objective; do not collapse current-value and reset-recovery checks into one numeric comparison.
Investigate implementation inconsistency only after ruling out different selectors, permitted adjustment, another Set and intervening reset.
- FID
- Feature Identifier
- NSID
- Namespace Identifier
3. Connect observations to specification conditions
Correct selector mistakes before diagnosing unexplained same-target inconsistency.
Track intervening configuration, resets and mode changes.
Sources: Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §5.2.13.1.18 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §5.2.13.1.18 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q300 Why might an AER completion have no matching visible log information?
Follow the explanation
A notice identifies a qualifying event, while the log may expose current state rather than a historical snapshot.
1. Preserve the evidence first
Match log scope to the event’s endpoint and entity.
Preserve event type, information, LID and required selectors.
- LID
- Log Page Identifier
A temperature warning may clear before a later SMART read without invalidating the earlier event.
2. Work through the possible causes
First check LID, scope and observation delay.
- LID
- Log Page Identifier
Read the matching log and check intervening acknowledgments and state changes.
3. Connect observations to specification conditions
A coherent timeline can explain cleared current state after a valid event.
Immediate, One-Shot and ordinary events have distinct clearing rules.
Preserve the first read and all acknowledgments before investigating persistent inconsistency.
Sources: Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §5.2.13–5.2.13.1.1 · Base 2.4 §5.2.13.1.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §5.2.13–5.2.13.1.1 · Base 2.4 §5.2.13.1.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q301 Does every failed CQE require a new error entry?
- CQE
- Completion Queue Entry
Follow the explanation
Error Information is not a mandatory one-entry copy of every failed CQE.
1. Preserve the evidence first
Match controller and error counts, considering overwrite by concurrent failures.
Inspect More and command-specific logging requirements.
More 1 indicates additional status information, while More 0 does not prohibit logging.
2. Work through the possible causes
First establish this error’s exact logging requirement strength.
Compare before/after counts and correlate valid entries by command identity and status.
3. Connect observations to specification conditions
Absence can be compliant where no applicable mandatory logging requirement exists.
Explicit mandatory details, such as specified capacity failures, override general optionality.
Exclude overwrite, reset clearing and incomplete reads before declaring a missing record.
4. Evidence supplied by the log
A successful CQE does not require a new Error Information entry. Read the complete conditions in this volume
Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q302 When do differing CQE, Error Information and PEL records conflict?
Follow the explanation
The three records have different purposes and timing, not bytewise equivalence.
1. Preserve the evidence first
CQEs describe commands, error entries add failure details and PEL describes persistent events.
Verify event support, More and command identity before correlating.
Matching error status bits 15:1 match CQE status; phase follows its separate rule.
2. Work through the possible causes
First establish what each record actually proves.
Correlate identity/time before parsing event-specific outcome fields.
3. Connect observations to specification conditions
Successful sanitize acceptance and later operation failure can both be correct.
Reused CIDs and requested-versus-completed values can create false contradictions.
Build an acceptance/start/operation-completion/query timeline.
Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q303 How are unexpected feature retention or lost saved values assessed?
Follow the explanation
Non-saveable does not mean nonpersistent, and unsaved current values need not survive power loss.
1. Identify the trigger and affected objects
Compare feature scope with actual reset coverage.
Preserve capabilities, value classes and the last successful Set’s save bit.
2. State changes and recovery
Namespace write protection has explicit retention despite being non-saveable.
Establish known saved state, apply a specific reset and requery the same target.
Pass criteria follow restoration rules and explicit exceptions, not universal zeroing.
3. Verify retention and recovery
Failed saves or intervening changes invalidate a simple lost-save diagnosis.
Record saveability, persistence, reset source and coverage separately.
First check the successful save and feature-specific exceptions.
Sources: Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q304 How are namespace changes reconciled across Identify, lists and AER?
Follow the explanation
Identify exposes current configuration, the changed list identifies changes and AER prompts rediscovery.
1. Preserve the evidence first
Controllers can observe different changes according to attachment and notification rules.
Record support/enables, pending requests and before/after inventories.
Attachment changes active inventory while creation changes allocated inventory.
2. Work through the possible causes
First identify the management operation class.
Perform one operation, observe completion/notice and rediscover current state.
3. Connect observations to specification conditions
A changed NSID need not still exist because deletion also requires rediscovery.
- NSID
- Namespace Identifier
Overflow uses FFFFFFFFh and requires full rediscovery, not treating it as a real namespace.
Preserve the first list and distinguish the initiating endpoint from notified peers.
Sources: Base 2.4 §5.2.24–5.2.25, 8.1.17–8.1.17.2 · Base 2.4 §5.2.13.1.5 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §5.2.13.1.14.2.6 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.24–5.2.25, 8.1.17–8.1.17.2 · Base 2.4 §5.2.13.1.5 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §5.2.13.1.14.2.6 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q305 How are unchanged firmware revision or slot fields assessed after activation?
Follow the explanation
Download, slot commit, scheduled activation and actual activation are distinct stages.
1. Preserve the evidence first
Slot/activation state may be shared within a domain.
Inspect capability, current/next active slots, slot revisions and current firmware revision.
Preserve action/slot/status and execute the specifically required activation reset.
2. Work through the possible causes
First verify action and activation mechanism.
Verify commit, perform activation and rediscover current state.
3. Connect observations to specification conditions
Equal version strings do not alone prove activation failure.
Fallback and requested PEL revision are not proof of active new firmware.
Reconcile pending/active slot, current revision and commit/reset events separately.
Sources: Base 2.4 §3.11–3.11.1, 5.2.9–5.2.10 · Base 2.4 §5.2.13.1.4 · Base 2.4 §5.2.13.1.14.2.2, 5.2.13.1.14.2.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.11–3.11.1, 5.2.9–5.2.10 · Base 2.4 §5.2.13.1.4 · Base 2.4 §5.2.13.1.14.2.2, 5.2.13.1.14.2.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q306 Is an in-progress log after sanitize command success an error?
Follow the explanation
Sanitize command completion acknowledges initiation, while media sanitization can continue in the background.
1. Preserve the evidence first
Match subsystem or namespace scope and result selection.
Inspect capabilities, command scope, status and supported completion events.
Interpret progress with operation and verification state, not FFFFh alone.
2. Work through the possible causes
First identify what the claimed completion actually establishes.
Preserve initiation completion and poll state, then correlate final result with any completion event.
3. Connect observations to specification conditions
In-progress after initiation is normal; final state must follow actual operation completion.
Exclude a newer operation, wrong scope and stale data before diagnosing a stuck status.
Correlate one operation across command, log, AER and PEL.
Sources: Base 2.4 §5.2.26–5.2.27 · Base 2.4 §5.2.13.1.38 · Base 2.4 §8.1.27.1–8.1.27.5 · Base 2.4 §5.2.13.1.14.2.9–5.2.13.1.14.2.10 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.26–5.2.27 · Base 2.4 §5.2.13.1.38 · Base 2.4 §8.1.27.1–8.1.27.5 · Base 2.4 §5.2.13.1.14.2.9–5.2.13.1.14.2.10 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q307 How is a missing result after self-test investigated?
Follow the explanation
Start-command success is not test success; current operation and result history establish the outcome.
1. Preserve the evidence first
Match controller/shared-test scope and read the complete log correctly.
Inspect support/options/time and LID 06h's 20 newest-first result slots.
Current state, progress, result code, test code and validity bits have distinct roles.
2. Work through the possible causes
First establish that a test actually started.
Capture history, run one test and compare the newest result after completion.
3. Connect observations to specification conditions
Result update and return to idle follow the specified ordering for a test that produces a result.
An Abort while idle can succeed without creating a test result.
Interpret reset effects using the distinct short/extended-test rules.
Sources: Base 2.4 §5.2.6, 8.1.8 · Base 2.4 §5.2.13.1.7 · NVM Command Set 1.3 §4.1.4.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.6, 8.1.8 · Base 2.4 §5.2.13.1.7 · NVM Command Set 1.3 §4.1.4.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q308 How are unexpected unsafe-shutdown counts assessed?
Follow the explanation
Count behavior depends on state at main-power loss, not only the requested shutdown type.
1. Preserve the evidence first
Base 2.4 UPL counts qualifying power losses, not host shutdown calls.
Preserve count, request, status and actual power-loss time.
Ordinary qualification concerns main-power loss before SHST10b, with a separate applicable out-of-band ignore-shutdown case.
2. Work through the possible causes
First establish actual main-power loss and SHST at that moment.
Read baseline, request shutdown, observe status and compare after controlled power cycling.
3. Connect observations to specification conditions
Abrupt shutdown can complete before power loss and need not increment UPL each time.
Incomplete normal shutdown may qualify, while controller reset without power loss does not automatically count.
Use pre-loss state rather than post-restart SHST.
Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §3.6–3.6.1 (memory-based scope and shutdown) · PCIe Transport 1.4 §3.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §3.6–3.6.1 (memory-based scope and shutdown) · PCIe Transport 1.4 §3.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q309 Which settings explain a warning change without an AER?
Follow the explanation
State transitions and event conditions differ; clearing a warning need not mirror assertion.
1. Preserve the evidence first
Aggregate and group-specific warnings use different scopes/settings.
Check support/enables, pending AERs and unacknowledged prior events.
Preserve warning bits, measured values and thresholds rather than only UI labels.
2. Work through the possible causes
First verify AEC at event time.
Verify qualifying conditions, competing/coalesced events and acknowledgment reads.
3. Connect observations to specification conditions
Qualifying enabled events follow their queuing rules, not one AER per sampled fluctuation.
No pending request means no immediate CQE; unconsumed completions are not missing notifications.
Correlate warning, configuration, requests and acknowledgments.
Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §4.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §4.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q310 How is apparent PEL event-order mismatch investigated?
Follow the explanation
Log order, event timestamp and real operation order are distinct.
1. Preserve the evidence first
Subsystem PEL can interleave controllers and permits defined vendor ordering.
Inspect reporting context, generation and clock origin/synchronization.
Host changes and restoration can move timestamps, so they are not universal monotonic sequence numbers.
2. Work through the possible causes
First verify context and event boundaries.
Read one consistent context, parse lengths and account for clock-change/reset events.
3. Connect observations to specification conditions
Newest-first is recommended with vendor-defined ordering allowed, not an unconditional mandate.
Mixed contexts and incorrect event-length accounting can create false disorder.
Use a host monotonic timeline as evidence without equating unsynchronized clocks.
Sources: Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding) · NVM Command Set 1.3 §4.1.4.4 · Base 2.4 §5.2.30.1.8 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding) · NVM Command Set 1.3 §4.1.4.4 · Base 2.4 §5.2.30.1.8 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q311 What evidence remains when CFS is set with little diagnostic information?
Follow the explanation
Fatal conditions may break diagnostics; absent logs do not invalidate CFS or justify unlimited further commands.
1. Preserve the evidence first
Distinguish fatal failure from a secondary controller’s Offline state.
Preserve accessible controller state, capabilities and recent management history.
Obtain available diagnostics without assuming every CFS cause has a readable dedicated record.
2. Work through the possible causes
First establish role and register-read validity.
Preserve evidence before reset/recovery, then query surviving records.
3. Connect observations to specification conditions
Reinitialize and verify recovery while retaining uncertainty about interrupted commands.
Unreliable/all-ones reads are not automatically valid NVMe state.
Separate device status, host timeout and communication-failure evidence.
Sources: Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §3.5.3–3.5.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.13.1.3 · Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding) · Base 2.4 §8.2.7 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §3.5.3–3.5.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.13.1.3 · Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding) · Base 2.4 §8.2.7 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q312 How are two observed completions after Abort classified?
Follow the explanation
Abort and its target each complete; two total CQEs can be normal, unlike duplicate target completion.
1. Preserve the evidence first
Identify commands by endpoint, SQID/CID and queue lifetime.
- SQID
- Submission Queue Identifier
- CID
- Command Identifier, unique among outstanding commands in one SQ
Record target identity, Abort’s own identity and IANP.
IANP semantics do not erase the target’s completion, and IANP1 permits later normal completion.
2. Work through the possible causes
First identify which completion belongs to Abort itself.
Separate Abort and target CQEs, then exclude host double-consumption.
3. Connect observations to specification conditions
Handle one completion for each command without assuming the target had no effects.
Two genuine completions for the same target in one lifetime violate single-completion tracking.
Exclude CID reuse and CQ wrap before declaring duplicates.
- CID
- Command Identifier, unique among outstanding commands in one SQ
- CQ
- Completion Queue
Sources: Base 2.4 §5.2.1 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.1 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q313 What is wrong with queue-memory access after completed deletion?
Follow the explanation
Access after the queue lifetime can corrupt memory already reused elsewhere.
1. Preserve the evidence first
Distinguish deleted queue memory from buffers belonging to other live commands.
Preserve target QID, successful deletion completion and memory range.
Submission is not successful deletion, and SQ/CQ dependencies differ.
- SQ
- Submission Queue
- CQ
- Completion Queue
2. Work through the possible causes
First establish successful deletion completion.
Check accesses after success and exclude legitimate address reuse by another queue.
3. Connect observations to specification conditions
After retirement, the controller must not continue using it as the deleted queue.
Such access can corrupt host data or produce invalid command/completion behavior.
Preserve reuse timing and queue identities; address equality alone is insufficient.
Sources: Base 2.4 §5.3.3–5.3.4 · Base 2.4 §5.3.1–5.3.2 · PCIe Transport 1.4 §3.4 (Command Related Resource Retirement) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.3.3–5.3.4 · Base 2.4 §5.3.1–5.3.2 · PCIe Transport 1.4 §3.4 (Command Related Resource Retirement) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q314 How should a CQE from before reset be handled?
Follow the explanation
Residual memory differs from a newly posted stale completion after reset.
1. Preserve the evidence first
Reset ends old queue lifetimes even when addresses and identifiers are reused.
Inspect reset source, readiness transitions, CQ initialization and expected phase.
Rebuild command tracking without associating an old CID with a new request.
2. Work through the possible causes
First verify phase and command-tracking initialization.
Finish reset and initialize memory before accepting valid new-lifetime completions.
3. Connect observations to specification conditions
Ignore stale completions while separately resolving possible prior media effects.
New writes to a retired queue require investigation, unlike passive residual bytes.
Correlate initialization and write timing to distinguish stale storage from late access.
Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · PCIe Transport 1.4 §3.3 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · PCIe Transport 1.4 §3.3 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q315 When can command success after detach be reasonable?
Follow the explanation
Submission acceptance is not successful execution, and some queries can address allocated inactive namespaces.
1. Preserve the evidence first
Detach affects selected endpoints, not every attached path.
Verify completed detach through both views.
Distinguish ordinary I/O from allocated-namespace queries and special management commands.
2. Work through the possible causes
First check endpoint and active-namespace requirement.
Submit a new command after successful detach on the detached endpoint.
3. Connect observations to specification conditions
Success on another attached path or an allowed allocated query can be normal.
Applicable inactive-namespace commands require Invalid Field absent an exception, distinct from invalid-NSID status.
Separate outstanding and newly submitted commands when assessing detach effects.
Sources: Base 2.4 §5.2.24–5.2.25, 8.1.17–8.1.17.2 · Base 2.4 §5.2.14.2.2–5.2.14.2.19, 5.2.14.3.1–5.2.14.3.2 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.24–5.2.25, 8.1.17–8.1.17.2 · Base 2.4 §5.2.14.2.2–5.2.14.2.19, 5.2.14.3.1–5.2.14.3.2 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q316 How is apparent Lockdown bypass investigated?
Follow the explanation
A prohibition matches interface, controller scope and command/feature target together.
1. Preserve the evidence first
Scope selectors jointly define the target, not opcode alone.
Read supported/current prohibitions under matching selectors.
Feature scope prohibits Set, not automatically Get; enhanced aggregate ACNTL0 is not no prohibition.
2. Work through the possible causes
First inspect interface, controller scope and command-versus-feature selection.
Test an exact matching target plus an allowed control after successful Lockdown.
3. Connect observations to specification conditions
A prohibited matching Admin command requires 0/23h.
Exclude expiry, later allowance, mismatched interfaces and explicit personality exceptions.
Correlate configuration, inventory and behavior under identical selectors.
Sources: Base 2.4 §5.2.16, 8.1.5 · Base 2.4 §5.2.13.1.20 · Base 2.4 §5.2.30.1.25.4–5.2.30.1.25.4.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.16, 8.1.5 · Base 2.4 §5.2.13.1.20 · Base 2.4 §5.2.30.1.25.4–5.2.30.1.25.4.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q317 How is excessive power-state recovery latency measured correctly?
Follow the explanation
Command latency includes exit, possible entry and execution, not only EXLAT.
1. Preserve the evidence first
Establish source/target states and concurrent thermal constraints.
Read state types, entry/exit latencies and selected policies.
ITPT is idle time in milliseconds; entry/exit latencies are in microseconds.
2. Work through the possible causes
First verify units and timing origin.
Separate idle, transition trigger, recovery and command execution timing.
3. Connect observations to specification conditions
Assess relevant transitions rather than equating full read latency with EXLAT.
CQE timing alone may not isolate an exit-latency violation.
Compare an operational baseline with matching workload, temperature and settings.
Sources: Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.13.1.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.13.1.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q318 How are three reset types compared for one feature?
Follow the explanation
Compare matched initial states under distinct reset mechanisms.
1. Identify the trigger and affected objects
Reset coverage and persistence conditions differ across the three cases.
Select one function and capture support, state and affected endpoints.
2. State changes and recovery
Track registers, queues, settings, ongoing operation and stored data separately.
Reset from matched baselines and restore query access before comparison.
Extended self-test persistence and I/O queue invalidation can coexist under CLR.
3. Verify retention and recovery
CC.EN-specific register exceptions do not cover all CLR, and subsystem reset is not factory restoration.
Tie differences to explicit rules and retain limits where behavior is unspecified.
First identify the actual reset trigger.
Sources: Base 2.4 §3.7.1–3.7.4 · PCIe Transport 1.4 §3.3 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.6–3.6.1 (memory-based scope and shutdown) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.7.1–3.7.4 · PCIe Transport 1.4 §3.3 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.6–3.6.1 (memory-based scope and shutdown) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q319 How is an operation’s real scope established?
Follow the explanation
Submission through one Admin Queue does not limit effects to that controller.
1. Preserve the evidence first
Commands and selectors determine namespace, controller, group, domain or subsystem effects.
Inspect command selectors, feature scope, capabilities and command effects.
Broadcast semantics are command-specific and effects metadata does not replace explicit scope definitions.
2. Work through the possible causes
First read special selector values for that specific command.
Identify endpoint, targets and shared resources, then observe inside/outside controls.
3. Connect observations to specification conditions
Detaching one endpoint does not duplicate or delete shared namespace data.
Exclude shared-resource and concurrent-operation causes before alleging out-of-scope effects.
Compare matching entities and times; active inventories can legitimately differ by endpoint.
Sources: Base 2.4 §5.2.13.1.6 · Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.14.2.2–5.2.14.2.19, 5.2.14.3.1–5.2.14.3.2 · Base 2.4 §3.2.2–3.2.3, 3.8 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.13.1.6 · Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.14.2.2–5.2.14.2.19, 5.2.14.3.1–5.2.14.3.2 · Base 2.4 §3.2.2–3.2.3, 3.8 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q320 How are the interfaces combined into one conformance investigation?
Follow the explanation
Build traceable evidence across advertisement, prerequisites, operation, result, notice, record and persistence.
1. Preserve the evidence first
Define one function and its scope before testing multiple interacting mechanisms.
Capture discovery, effects and relevant configuration as the baseline.
Record request, completion and applicable logs/events, explaining inapplicable or unsupported interfaces.
2. Work through the possible causes
First state one precise requirement and then select the evidence needed to test it.
Run a valid case, isolate invalid conditions and then test persistence from matched baselines.
3. Connect observations to specification conditions
Conclusions identify supported requirements and remaining evidence limitations.
Do not turn permissions into mandates, invent statuses for undefined behavior or equate acceptance with background completion.
Link raw evidence on a timeline with source sections, figures and PDF pages.
Sources: Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.13.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.13–5.2.13.1.1 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.13.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.13–5.2.13.1.1 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Shared rules linked from the answers
Each shared mechanism is explained in full once in this volume. Use browser Back to return to the question; explicit command or feature exceptions take precedence.
Command completion, events and records · Are Error Information or other logs updated?
A successful CQE does not require a new Error Information entry. For an error with More=1, read LID 01h and correlate SQID, CID and Error Count; not every unsuccessful CQE requires a new entry. Re-read the interfaces named in this question for the state the operation changes.
- SQID
- Submission Queue Identifier
Source locations and existing figure guides
Base printed page = PDF page−26; the other two use identical numbers. Locations follow the supplied PDF body and retain figure numbers. Shared pages contribute only the relevant definitions, excluding Fabrics and PCIe link/packet content.
- Base 2.4 · §3.1.4 (CC, CSTS, NSSR)
Printed pages 60–66 · PDF 86–92 · Figure 41–43 - Base 2.4 · §3.2.2–3.2.3, 3.8
Printed pages 80–84, 125–129 · PDF 106–110, 151–155 · Figure 67–69, 86–89 - Base 2.4 · §3.5.3–3.5.4
Printed pages 109–113 · PDF 135–139 · Figure 84–85 - Base 2.4 · §3.6–3.6.1 (memory-based scope and shutdown)
Printed pages 113–115 · PDF 139–141 · Figure 85 - Base 2.4 · §3.7.1–3.7.4
Printed pages 120–124 · PDF 146–150 - Base 2.4 · §3.11–3.11.1, 5.2.9–5.2.10
Printed pages 135–138, 202–206 · PDF 161–164, 228–232 · Figure 187–193 - Base 2.4 · §4.2.1, 4.2.3–4.2.4
Printed pages 144–157 · PDF 170–183 · Figure 97–105, 109 - Base 2.4 · §4.2.3
Printed pages 145–155 · PDF 171–181 · Figure 101–105 - Base 2.4 · §4.4
Printed pages 166–169 · PDF 192–195 · Figure 126–127 - Base 2.4 · §5.2.1
Printed pages 181–182 · PDF 207–208 · Figure 147–149 - Base 2.4 · §5.2.2
Printed pages 183–190 · PDF 209–216 · Figure 150–156 - Base 2.4 · §5.2.2 (PCIe-applicable events)
Printed pages 183–191 · PDF 209–217 · Figure 150–160 - Base 2.4 · §5.2.6, 8.1.8
Printed pages 199–201, 614–616 · PDF 225–227, 640–642 · Figure 176–180, 700–701 - Base 2.4 · §5.2.13–5.2.13.1.1
Printed pages 212–218 · PDF 238–244 · Figure 203–211 - Base 2.4 · §5.2.13.1.2
Printed pages 218–220 · PDF 244–246 · Figure 212 - Base 2.4 · §5.2.13.1.3
Printed pages 220–225 · PDF 246–251 · Figure 213–214 - Base 2.4 · §5.2.13.1.4
Printed pages 225–226 · PDF 251–252 · Figure 215 - Base 2.4 · §5.2.13.1.5
Printed pages 226 · PDF 252 - Base 2.4 · §5.2.13.1.6
Printed pages 226–229 · PDF 252–255 · Figure 216–217 - Base 2.4 · §5.2.13.1.7
Printed pages 229–232 · PDF 255–258 · Figure 218–219 - Base 2.4 · §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Printed pages 244–256, 258, 262–264 · PDF 270–282, 284, 288–290 · Figure 232–244, 246, 252–253 - Base 2.4 · §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding)
Printed pages 244–256, 258 · PDF 270–282, 284 · Figure 232–244, 246 - Base 2.4 · §5.2.13.1.14.2.2, 5.2.13.1.14.2.4
Printed pages 252–255 · PDF 278–281 · Figure 238, 240–241 - Base 2.4 · §5.2.13.1.14.2.6
Printed pages 258–259 · PDF 284–285 · Figure 247 - Base 2.4 · §5.2.13.1.14.2.9–5.2.13.1.14.2.10
Printed pages 261–262 · PDF 287–288 · Figure 250–251 - Base 2.4 · §5.2.13.1.18
Printed pages 276–278 · PDF 302–304 · Figure 270–271 - Base 2.4 · §5.2.13.1.20
Printed pages 279–283 · PDF 305–309 · Figure 274–278 - Base 2.4 · §5.2.13.1.38
Printed pages 313–320 · PDF 339–346 · Figure 312 - Base 2.4 · §5.2.14.2.1
Printed pages 340–387 · PDF 366–413 · Figure 338–341 - Base 2.4 · §5.2.14.2.1 (Power State Descriptor)
Printed pages 384–387 · PDF 410–413 · Figure 340–341 - Base 2.4 · §5.2.14.2.2–5.2.14.2.19, 5.2.14.3.1–5.2.14.3.2
Printed pages 387–399, 402–404 · PDF 413–425, 428–430 · Figure 342–355, 360–362 - Base 2.4 · §5.2.16, 8.1.5
Printed pages 405–408, 597–599 · PDF 431–434, 623–625 · Figure 365–367 - Base 2.4 · §5.2.24–5.2.25, 8.1.17–8.1.17.2
Printed pages 444–448, 660–663 · PDF 470–474, 686–689 · Figure 442–450 - Base 2.4 · §5.2.26–5.2.27
Printed pages 448–454 · PDF 474–480 · Figure 451–455 - Base 2.4 · §5.2.30.1 (common fields, scope and persistence)
Printed pages 456–460 · PDF 482–486 · Figure 463–466 - Base 2.4 · §5.2.30.1.2, 5.2.30.1.7
Printed pages 460–462, 468–469 · PDF 486–488, 494–495 · Figure 468–469, 475–478 - Base 2.4 · §5.2.30.1.8
Printed pages 469–471 · PDF 495–497 · Figure 479–480 - Base 2.4 · §5.2.30.1.25.4–5.2.30.1.25.4.1
Printed pages 493–494 · PDF 519–520 · Figure 518–519 - Base 2.4 · §5.3.1–5.3.2
Printed pages 527–531 · PDF 553–557 · Figure 571–579 - Base 2.4 · §5.3.3–5.3.4
Printed pages 531–532 · PDF 557–558 · Figure 580–583 - Base 2.4 · §8.1.19.1–8.1.19.5
Printed pages 666–671 · PDF 692–697 · Figure 738–741 - Base 2.4 · §8.1.27.1–8.1.27.5
Printed pages 711–732 · PDF 737–758 · Figure 770–779 - Base 2.4 · §8.2.7
Printed pages 754–758 · PDF 780–784 · Figure 796 - Base 2.4 · §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2)
Printed pages 825–828 · PDF 851–854 - NVM Command Set 1.3 · §4.1.4.3
Printed pages 75–76 · PDF 75–76 · Figure 111 - NVM Command Set 1.3 · §4.1.4.4
Printed pages 76–77 · PDF 76–77 · Figure 112 - PCIe Transport 1.4 · §3.3
Printed pages 11–12 · PDF 11–12 - PCIe Transport 1.4 · §3.4 (Command Related Resource Retirement)
Printed pages 13 · PDF 13
When you need a field guide
Existing figure explanations have canonical locations; use these links instead of duplicating the same guide.
- Base 2.4 Figure 101 · Completion Queue Entry: Status Field
- Base 2.4 Figure 104 · Status Code – Command Specific Status Values
- Base 2.4 Figure 338 · Identify – Identify Controller Data Structure, I/O Command Set Independent
- Base 2.4 Figure 41 · Offset 14h: CC – Controller Configuration
- Base 2.4 Figure 42 · Offset 1Ch: CSTS – Controller Status
- Base 2.4 Figure 97 · Common Completion Queue Entry Layout – Admin and All I/O Command Sets
Original documents used
- NVM Express Base Specification · Revision 2.4 · 2026-07-31
NVM-Express-Base-Specification-Revision-2.4-Ratified-2026.07.31.pdf - NVM Express NVM Command Set Specification · Revision 1.3 · 2026-07-31
NVM-Express-NVM-Command-Set-Specification-Revision-1.3-Ratified-2026.07.31.pdf - NVM Express NVMe over PCIe Transport Specification · Revision 1.4 · 2026-07-31
NVM-Express-NVMe-over-PCIe-Transport-Specification-Revision-1.4-Ratified-2026.07.31.pdf


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