1. What differs

HMB is host memory dedicated to the controller; CMB is controller memory for supported uses; PMR is directly accessible persistent memory.

HMB uses FID 0Dh descriptors; CMB uses address/control registers; PMR uses enable/readiness/health registers.

FID

Feature Identifier

2. How to choose and verify

Discover HMB through HMPRE, CMB through CAP/CMBSZ and PMR through CAP/PMRCAP.

Match the need: firmware host RAM, supported CMB SQ placement or persistent PMR data with barriers and health checks.

SQ

Submission Queue

Success means supported use within its constraints, not universal placement freedom.

3. Conditions that shape the comparison

Queue/list use in PMR is outside scope and may return Invalid Field; writable PMR is not interchangeable with CMB.

Compare support, configuration, access method and restored contents, not only readable bytes.

1. Establish the source and scope

The allocation is exclusive to one controller and unavailable for ordinary host writes while enabled.

Read preferred/minimum size, minimum descriptor size and maximum descriptors; size capability fields use 4 KiB units.

2. Fields, units and worked interpretation

HSIZE/BSIZE use CC.MPS pages; HMDLEC is a literal count, list address is 16-byte aligned and BADD page-aligned.

Pin memory, construct descriptors, reconcile sizes and enable with EHM=1, awaiting success.

Get verifies allocation; with hypothetical 8 KiB pages, HSIZE256 means 2 MiB.

3. Conditions that change the interpretation

Zero HMDLEC requires Invalid Field; exceeding usable descriptor limits may reduce utilization rather than force rejection.

Convert capability units before encoding HSIZE and verify readback.

1. Distinguish the failure conditions

Check list structure, ranges and current enable state.

Zero entry count is Invalid Field; zero-size descriptors are ignored. The list address low four bits are treated as zero without a required check.

Re-enabling active HMB requires Command Sequence Error; unsupported HMNARE requires Invalid Field. Do not demand one status for every alignment defect.

2. Establish the cause from evidence

Check limits, HMBR, current EHM and submitted fields.

Separate specified format errors from inaccessible-memory transfer failures.

3. Outcome and follow-up checks

Valid allocation succeeds; out-of-limit allocation may be only partly used.

Match each condition to its rule, preserving ignore versus reject semantics.

First check whether multiple faults prevent a unique expected status.

1. Prepare the operation

EHM controls use; MR describes whether returned contents are unchanged.

Read EHM/allocation rather than assuming pre-reset enablement persists.

EHM0 ignores CDW12–15; MR1 requires identical size, list address/content and buffer contents.

2. Sequence and completion conditions

CQE

Completion Queue Entry

3. Handle unmet conditions

Re-enable while enabled is a sequence error; claiming MR1 after modification violates the return premise.

1. Mechanism and scope

Damage may reach unrelated host data in reassigned physical pages.

Both descriptors and described ranges must remain intact; retaining only the list is insufficient.

2. Understand it through actions and results

Check EHM, disable completion and allocation/mapping lifetime.

Disable and await success before unmapping; failure recovery must end old accesses before reclamation.

After a valid handoff the old allocation is no longer accessed.

3. Avoid a misleading conclusion

Host misuse has no guaranteed detection or fixed status and may corrupt data; error logging is not protection.

Distinguish premature host reclamation from controller accesses after successful disable.

1. Select the target and information

Its PCIe and controller address ranges may have different bases but matching offsets.

Check CAP.CMBS, enable CRE and read location/size; zero values with CRE0 do not prove absence.

BIR selects BAR, OFST locates the region and SZ×SZU determines size within BAR limits; support bits distinguish uses.

BAR

Base Address Register

2. Query sequence and interpretation

Configure a nonconflicting CBA, enable CMSE, check CBAI and initialize contents.

Both address views reach the same contents at matching offsets.

3. Handle missing or inconsistent evidence

Invalid CBA sets CBAI and prevents memory-space enablement; it is register state, not an Admin CQE.

Cross-check address bounds, units and use flags, not just capability presence.

First check confusion between BAR and configured controller addresses.

1. Mechanism and scope

Restrictions apply to an entire queue, a command’s list or its data/metadata set.

CQMMS0 prohibits mixed queue placement; CQPDS0 requires contiguous queues. LISTS and related bits govern pointer-list placement and dependencies.

2. Understand it through actions and results

Inspect use flags and mixed-memory/discontiguous-list capabilities.

Select the object capability, then validate its combined placement constraints before allocating.

With hypothetical SQS1/CQS0, an SQ may use CMB while its CQ remains in host memory.

CQ

Completion Queue

3. Avoid a misleading conclusion

General misuse requires Invalid Use of CMB; placing lists with LISTS0 is explicitly undefined, not a fixed-status case.

Interpret RDS/WDS by command transfer direction.

1. Distinguish the failure conditions

CBA/size define the controller range; disabled CMSE routes addresses elsewhere.

CBA must not overflow the 64-bit address space or overlap enabled PMR space.

Mapping failure uses CBAI; misuse uses its specified status. Out-of-range addresses may resolve elsewhere and have no universal CMB-overrun status.

2. Establish the cause from evidence

Preserve mapping/status/capabilities and the full command range.

Calculate both range endpoints, resolve address spaces and check use/mixing rules.

3. Outcome and follow-up checks

Valid ranges and uses follow ordinary command processing.

Command outcomes and register status are separate evidence.

First check arithmetic overflow and which address space was used.

1. Identify the trigger and affected objects

CC.EN reset and FLR explicitly retain CMBMSC; other sources use their own register rules.

FLR

Function Level Reset

Snapshot source and registers, then reread after recovery.

2. State changes and recovery

CMSE0→1, Controller Reset and FLR make CMB contents undefined.

FLR

Function Level Reset

Restore mapping, initialize memory and rebuild queues, especially CQ phase bits.

A new lifetime uses initialized contents, not old queue state.

3. Checks across reset or power loss

4. Verify retention and recovery

Identical residual bytes do not turn undefined retention into a guarantee.

Validate mappings and content/queue initialization separately.

First check whether unchanged CMBMSC incorrectly caused initialization to be skipped.

1. Prepare the operation

PMR occupies the selected BAR region, with separately configurable controller addressing.

Check support, location, command access, barrier mechanisms and timeout units.

EN1 plus NRDY0 establishes readiness, with health/error checks still required.

2. Sequence and completion conditions

3. Handle unmet conditions

PMRTO is a transition wait allowance, not a per-command timeout; invalid addressing is reported by CBAI.

1. Distinguish the failure conditions

Direct accesses and commands using PMR buffers expose errors differently.

Not-ready reads can succeed with undefined data and writes can succeed without updating memory; health distinguishes restore failure, read-only and unreliable states.

Detected failure writing an associated PMR should produce Data Transfer Error for the command; direct accesses have no NVMe CQE.

2. Establish the cause from evidence

Inspect EN/NRDY/HSTS/ERR; HSTS clears when not ready, so zero alone does not prove usable health.

Establish readiness, access, then verify barriers/status and reconsider accesses since the last normal health observation.

3. Outcome and follow-up checks

A successful NVMe command targeting PMR does not alone prove the PMR write succeeded.

Validate command success and PMR health separately.

First inspect readiness at access time, not merely after later recovery.

1. Prepare the operation

Coordinate direct users and commands still using PMR buffers.

Check supported barriers, health and transition wait units.

Use the advertised PMR-read or PMRSTS-read barrier, not an arbitrary register read.

2. Sequence and completion conditions

Stop accesses, drain users, perform the supported barrier/health check, clear EN and wait for NRDY1.

NRDY1 indicates disabled readiness for re-enable; valid persistent content is not made undefined as CMB would be.

3. Handle unmet conditions

Successful disable cannot prove earlier data valid when error/health state says otherwise.

Verify barrier/health and enable-state ordering, not only final EN0.

1. Identify the trigger and affected objects

Retention applies to completed persistent writes, not unverified in-flight writes.

Preserve barrier evidence and inspect enable/readiness/health/mapping after recovery.

2. State changes and recovery

Restore Error means current normal persistent operation with possibly incorrect restored content, unlike ongoing Unreliable status.

Restore readiness, inspect health and verify content, accounting separately for Sanitize.

Qualified persistent data survives CLR, disable and power cycle; register retention remains source-specific.

3. Checks across reset or power loss

4. Verify retention and recovery

Nonzero ERR persists until PCI Function reset; clearing CC.EN does not necessarily clear it.

Verify data, registers and errors as separate requirements.

First distinguish persistent-data loss from incomplete writes or premature reads.

1. What differs

Ordinary host buffers are command-scoped; HMB is controller-exclusive; CMB is device-local; PMR adds persistence mechanisms.

Reclaim ordinary buffers by command/queue lifetime, HMB after disable, initialize CMB after reset and verify PMR barriers/health.

2. How to choose and verify

Use capabilities and command pointers to identify the actual space.

Map host/controller addresses to physical memory and mark access/reclamation boundaries.

A Write completion can end source-buffer use without releasing HMB or performing a PMR barrier.

3. Conditions that shape the comparison

Error outcomes depend on the violated interface, not one universal memory-error status.

Verify ownership, mapping, completion and persistence rather than merely readable contents.