NVMe Self-Study Bank: Admin and I/O queues
NVMe · Q1–328
Q10–Q21
Admin and I/O queues
Queue memory, allocated queue counts and successfully created queues are distinct. Learn SQ/CQ dependencies before size, identifiers, deletion and reset so memory can be reclaimed at the right time.
Each question is followed by its explanation. Start with the volume overview, then follow the field interpretations, comparisons or processes. Essential conditions and the normal path are visible from the start. All numerical examples are hypothetical. Status is written SCT/SC; h indicates hexadecimal.
- SCT
- Status Code Type
One CQ and two SQs: creation and reclamation run in opposite directions
The CQ is the completion destination for its SQs; it cannot be deleted while an SQ still depends on it.
| Observation | Hypothetical value | What it establishes |
|---|---|---|
| Count allocation | FID 07h returns NSQA=3, NCQA=1 | 4 I/O SQs and 2 I/O CQs allocated, not created |
| Queue depth | Create CQ: QID=1, QSIZE=7 | 8 entries; the ring reserves one slot to distinguish full |
| Dependencies | SQ1.CQID=1; SQ2.CQID=1 | Create CQ1 before SQ1 and SQ2 |
| Reclamation | Delete SQ1/SQ2 and wait for their successful completions | Delete CQ1 next; reclaim memory after the relevant lifetime ends |
- FID
- Feature Identifier
- CQID
- Completion Queue Identifier
Worked interpretation: If SQ1 is deleted but SQ2 remains, deleting CQ1 is still an invalid sequence: SQ2 still uses it. SQ1 deletion also does not authorize reclaiming SQ2 data buffers.
Sources: Base 2.4 §5.2.30.1.5 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §5.3.3–5.3.4 · Base 2.4 §3.3.1
Review the terminology when needed
- Controller / namespace
- A controller receives commands and manages access. A namespace is a logical storage space that commands can address. An NVM subsystem contains controllers and nonvolatile storage resources.
- SQ / CQ / SQE / CQE
- Submission and Completion Queues carry command entries (SQEs) and completion entries (CQEs). QID identifies a queue, CID distinguishes outstanding commands in one SQ, and NSID identifies a namespace.
- Register / Identify / Feature / Log
- A register exposes control or state. Identify queries capabilities and attributes; features query or configure operation; log pages report specific state or records. FID, LID, CNS and CSI select features, logs, Identify structures and command sets.
- index / offset / zero-based
- An index selects an entry, usually starting at 0; an offset measures distance from an origin in specified units. A zero-based count encodes count−1, but not every zero-valued field is a count. A Dword is 4 bytes; a byte is 8 bits.
- Scope / reset / retention
- Scope names the affected objects; retention means preserving state. Controller Reset (clearing CC.EN) is one form of Controller Level Reset, or CLR. Different CLR triggers can retain different registers.
Questions in this volume
- Q10 · How are the Admin Submission and Completion Queues established through AQA, ASQ and ACQ?
- Q11 · What are the size, base-address and page-alignment requirements for Admin and I/O queues?
- Q12 · How are I/O CQs and SQs created, and why must the CQ be created first?
- Q13 · How does sharing a CQ differ from giving every SQ its own CQ?
- Q14 · How does the host determine supported queue memory layouts?
- Q15 · Which statuses apply to duplicate/zero QIDs, missing CQIDs, oversized queues and invalid vectors?
- Q16 · How do Number of Queues results relate to queues that can actually be created?
- Q17 · Why must associated SQs be deleted before their CQ?
- Q18 · What happens when deleting a missing queue, a referenced CQ or an SQ with outstanding commands?
- Q19 · May the controller access deleted queue memory or post completions for its old commands?
- Q20 · What is the scope of Queue Level Reset, and how is outstanding work handled?
- Q21 · Are old I/O queues valid after Controller Reset, and what must the host do again?
Q10 How are the Admin Submission and Completion Queues established through AQA, ASQ and ACQ?
Follow the explanation
Establish the management channel before using Create I/O Queue. An absent Admin queue cannot create itself through a command.
1. Prepare the operation
Each controller has an Admin SQ/CQ with QID=0, separate from I/O queue identifiers.
AQA gives both lengths; ASQ/ACQ give their physical bases. Admin queues require physical contiguity and are not created with a PC=0 Create Queue PRP list.
- PRP
- Physical Region Page, a data-page pointer
ASQS/ACQS are zero-based: 64 entries encode as 63. Admin SQEs are 64 bytes and CQEs 16 bytes; the two queues need not have equal lengths.
2. Sequence and completion conditions
Allocate and initialize memory, write the three registers with EN=0 and clear Admin CQ phases. Configure CC, enable, wait for RDY=1, then submit the first Admin command.
Identify can be submitted and matched by CID in Admin CQ. ACQ is associated with interrupt vector 0, while the host can also poll phase tags.
- CID
- Command Identifier, unique among outstanding commands in one SQ
3. Handle unmet conditions
Size=0 encodes one slot and is not a legal way to disable an Admin queue; enabling in that configuration is undefined. Delete I/O Queue cannot delete Admin queues.
Compare AQA, allocated memory and the first CQE. Correct register readback does not establish device access to the supplied memory.
- CQE
- Completion Queue Entry
Sources: Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §3.5.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1
Source locations for this question
Sources: Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §3.5.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1
Q11 What are the size, base-address and page-alignment requirements for Admin and I/O queues?
Follow the explanation
Keep entry counts, byte sizes and memory pages distinct, and prevent a queue from exceeding allocated memory.
1. Establish the source and scope
Distinguish Admin/I/O and host-memory/CMB configurations. A rule for one is not automatically universal.
- CMB
- Controller Memory Buffer
Check AQA for Admin, and CAP.MQES/CQR and CC.IOSQES/IOCQES for I/O. CMB exceptions depend on CMBLOC.CQDA/CQPDS and CMBSZ queue support.
- CMB
- Controller Memory Buffer
2. Fields, units and worked interpretation
Length fields encode entries−1. Ordinary bases and each PRP page of a discontiguous queue align to CC.MPS; PRP1 has offset zero.
- PRP
- Physical Region Page, a data-page pointer
Choose slots and entry size, calculate bytes, allocate pages and a PRP list if supported, then Create. Do not alter a queue's live PRP list.
Minimum size is two slots; Admin maximum is 4096 and I/O maximum min(65536, MQES+1). One slot remains unavailable to distinguish full from empty.
3. Conditions that change the interpretation
For zero or unsupported I/O QSIZE, the specification recommends Invalid Queue Size (1/02h); a nonzero PRP offset should return PRP Offset Invalid (0/13h). Apply the specific SQ/CQ requirement for PC violating CQR.
A 128-slot NVM SQ needs 8192 bytes, its CQ 2048 bytes. Equal QSIZE=127 does not imply equal byte allocations.
Sources: Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.3.3–3.4.1 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.3.3–3.4.1 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q12 How are I/O CQs and SQs created, and why must the CQ be created first?
Follow the explanation
Every I/O needs a valid completion destination. Create the CQ before its SQ: this is an ordering requirement, not merely a performance recommendation.
1. Prepare the operation
An SQ selects its CQ at creation; several SQs may use one existing CQ.
Base 2.4 recommends using Set Features Number of Queues during initialization. Also check MQES/CQR, entry sizes and interrupt-vector limits; Create fields remain subject to their applicable requirements. The recommended initialization sequence and individual field requirements have different normative strengths.
Create CQ uses PRP1, QID, QSIZE, PC, IEN and IV. Create SQ additionally uses CQID, QPRIO and NVMSETID; zero NVMSETID means no specific set association.
2. Sequence and completion conditions
Each arrow requires completion of the preceding step, not merely submission order.
- Prepare CQ memory
Allocate with the required size and alignment, and initialize CQE phase bits.
- Create I/O CQ → await success on the Admin CQ
This Create completes on the Admin CQ, not on the new I/O CQ.
- Create I/O SQ → await success on the Admin CQ
CQID refers to the successfully created CQ. Both successful Creates report SCT=0, SC=00h.
- Start I/O
Only after both steps succeed, populate I/O SQEs and update the SQ Tail Doorbell.
If CQ creation fails, that CQ is not available to the SQ. Resolve the failure; submitted is not the same as successfully created.
- CQE
- Completion Queue Entry
- SCT
- Status Code Type
3. Handle unmet conditions
An in-range CQID that has not been created returns Completion Queue Invalid (1/00h); CQID=0 or out of range returns Invalid Queue Identifier (1/01h).
Match CQID against the host's SQ-to-CQ map. Creating a CQ does not automatically associate every SQ with it.
Sources: Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.3.1 · Base 2.4 §5.2.30.1.5 · Base 2.4 §3.5.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.3.1 · Base 2.4 §5.2.30.1.5 · Base 2.4 §3.5.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q13 How does sharing a CQ differ from giving every SQ its own CQ?
Follow the explanation
Trade resource usage against completion-path isolation. Shared CQs reduce CQ resources but concentrate completion traffic.
1. What differs
Completion slots and CQ notification are shared; the SQs do not become one CID namespace.
- CID
- Command Identifier, unique among outstanding commands in one SQ
CQE.SQID+CID identifies the original command; SQHD updates consumption for that SQ.
- SQID
- Submission Queue Identifier
2. How to choose and verify
Number of Queues returns separate SQ/CQ allocations. Create SQ.CQID selects the mapping; CQ.IEN/IV configures notification.
Create the CQ and multiple SQs referencing it. Dispatch each CQE by SQID, then advance the shared CQ head.
- SQID
- Submission Queue Identifier
SQ1/CID 7 and SQ2/CID 7 may coexist and must be matched separately, unlike reusing an outstanding CID within one SQ.
3. Conditions that shape the comparison
Valid sharing is not an error. Missing CQIDs follow Create SQ status rules; a full shared CQ does not automatically produce Invalid Queue Size for each SQ.
Compare completion capacity, submission traffic and host consumption rate; SQ count alone does not establish freedom from bottlenecks.
Sources: Base 2.4 §3.3.1 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.3.1 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q14 How does the host determine supported queue memory layouts?
Follow the explanation
Describe queue memory in a layout the controller supports. Virtual contiguity does not establish physical contiguity.
1. Select the target and information
Admin queues require physical contiguity. Discontiguous I/O queues depend on CAP.CQR and memory location.
CQR=1 requires physical contiguity; CQR=0 allows discontiguous I/O queues. CMB placement additionally requires CMBSZ.SQS/CQS and CMBLOC.CQPDS/CQDA checks.
With Create I/O Queue.PC=1, PRP1 is the queue base; with PC=0 it points to a queue-page PRP list, distinct from ordinary data-transfer PRP2 rules.
2. Query sequence and interpretation
Confirm placement/support, build a complete aligned page list and Create. Retain the list's address and contents until successful deletion or reset.
The controller fetches SQEs/writes CQEs through the chosen layout. Successful Create does not authorize rearranging its pages while live.
3. Handle missing or inconsistent evidence
For CQR=1 and PC=0, Create CQ shall return Invalid Field (0/02h), while Create SQ says should. Unsupported CMB usage may return Invalid Use of Controller Memory Buffer (0/12h).
Cross-check CQR, PC, PRP1 interpretation and actual page layout, rather than validating only the completion.
First ask whether PRP1 addresses queue storage or its page list. Confusing them breaks the layout even with valid addresses.
Sources: Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q15 Which statuses apply to duplicate/zero QIDs, missing CQIDs, oversized queues and invalid vectors?
Follow the explanation
Match distinct parameter errors to their defined statuses instead of flattening them into Invalid Field.
1. Distinguish the failure conditions
This concerns Create I/O Queue Admin commands. Duplicate QIDs are checked within the SQ or CQ identifier space respectively.
Inspect QID, CQID, QSIZE and IV, and initialization of IOSQES/IOCQES. The relevant parameters are in CDW10/11.
Duplicate/zero/out-of-range QID should return 1/01h; zero/unsupported QSIZE should return 1/02h. Create SQ shall return 1/00h for an in-range uncreated CQID, or 1/01h for zero/out-of-range CQID. An IV exceeding the range in Transport 1.4 Figure 7 should return 1/08h. Unless specified otherwise, implementations choose among simultaneously applicable errors.
2. Establish the cause from evidence
CAP.MQES, Number of Queues allocations and PCIe interrupt configuration establish legal ranges.
For a learning test, change one condition at a time from a valid baseline; multiple errors can obscure the expected result.
3. Outcome and follow-up checks
Valid parameters successfully create the queue; after failure, do not treat the requested QID as created.
When available, Error Information Parameter Error Location can identify the field. Without More=1, do not assume every such error must have an entry.
First check that only one field is invalid and the expected SCT is 1, rather than comparing SC alone.
Sources: Base 2.4 §5.3.1–5.3.2 · Base 2.4 §4.2.3 · PCIe Transport 1.4 §3.5 · PCIe Transport 1.4 §3.1–3.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.3.1–5.3.2 · Base 2.4 §4.2.3 · PCIe Transport 1.4 §3.5 · PCIe Transport 1.4 §3.1–3.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q16 How do Number of Queues results relate to queues that can actually be created?
Follow the explanation
Obtain SQ/CQ allocations before creating queues. Allocation is neither an instantiated queue nor queue depth.
1. Establish the source and scope
FID 07h has controller scope and excludes Admin SQ/CQ.
- FID
- Feature Identifier
A successful Set Features FID 07h returns allocations in CQE DW0. A successful Get Features with SEL other than 011b also returns them; SEL=011b returns Supported Capabilities, not allocation counts. CAP.MQES separately limits per-queue depth.
2. Fields, units and worked interpretation
Requested NSQR/NCQR and returned NSQA/NCQA are zero-based. Allocations may be smaller or larger than requested because of allocation units.
If the host sets Number of Queues, the specification recommends doing so during initialization before creating any I/O queue. The first successful Set after Controller Level Reset (CLR) allocates the queues, and that allocation remains fixed until the next CLR.
DW0=00030007h allocates four CQs and eight SQs. Each still requires Create, with the respective QID ranges.
3. Checks across reset or power loss
| Trigger | Effect on this operation or state |
|---|---|
| What survives or continues after Controller Reset? | The first successful Set FID 07h after CLR allocates anew. Read the result and recreate queues rather than assuming the previous allocation. |
4. Conditions that change the interpretation
Setting after an I/O queue exists shall return Command Sequence Error (0/0Ch). Requested=FFFFh should return Invalid Field (0/02h). Subsequent Set before queue creation should succeed without changing allocation.
Compare allocations, the actual created-queue list and MQES. Allocated counts are not current existence counts.
Sources: Base 2.4 §5.2.30.1.5 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §5.2.13.1.18
Source locations for this question
Sources: Base 2.4 §5.2.30.1.5 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §5.2.13.1.18
Q17 Why must associated SQs be deleted before their CQ?
Follow the explanation
Prevent active SQs from losing their completion destination. For associated queues this is a required host deletion order.
1. Prepare the operation
A CQ may serve multiple SQs. Delete every associated SQ, not only an SQ with the same numeric QID.
Use the host's SQ-to-CQID map from creation. Number of Queues does not provide this association list.
Delete I/O SQ/CQ selects the target with CDW10.QID; both travel through Admin SQ.
2. Sequence and completion conditions
Stop submissions, appropriately drain work, delete each associated SQ and await success, process needed old completions, then delete the CQ.
Successful Delete CQ allows reclamation of its PRP list and queue resources. Successful Delete SQ separately establishes termination of processing for that SQ's commands.
3. Handle unmet conditions
Delete CQ with associated SQs shall return Invalid Queue Deletion (1/0Ch); zero or invalid QID returns Invalid Queue Identifier (1/01h).
Correlate successful deletion with memory reclamation. Merely submitting Delete does not authorize early reclamation of DMA memory.
- DMA
- Direct Memory Access, device access to memory
Sources: Base 2.4 §3.3.1 · Base 2.4 §5.3.3–5.3.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.3.1 · Base 2.4 §5.3.3–5.3.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q18 What happens when deleting a missing queue, a referenced CQ or an SQ with outstanding commands?
Follow the explanation
Distinguish an invalid deletion request from valid deletion terminating commands. Outstanding work does not itself make Delete SQ illegal.
1. Distinguish the failure conditions
SQ deletion affects its outstanding I/O; CQ deletion depends on the existence of every associated SQ.
Delete requires a valid nonzero QID; affected I/O commands retain their own SQID/CID identities.
Invalid QID: 1/01h. CQ still referenced: 1/0Ch. I/O aborted by SQ deletion uses 0/08h, including implicit completion established by successful Delete.
2. Establish the cause from evidence
Consult host creation/deletion and outstanding-command records. These are runtime state, not Identify optional capabilities.
Drain before normal teardown. On successful Delete SQ, previously submitted commands for which the controller had not posted a CQE are implicitly aborted. A CQE already posted but not yet read by the host remains an explicit completion.
3. Outcome and follow-up checks
Before successful Delete SQ, original commands may complete normally or with abort status. After success, no further completions may be posted for those commands.
Distinguish commands whose CQEs were posted before successful Delete from commands implicitly aborted without posted CQEs. A host-read log alone may miss an already posted CQE, so absence of a read is insufficient.
First check whether Delete SQ itself completed successfully. Its outstanding state does not establish that all original work stopped.
Sources: Base 2.4 §5.3.3–5.3.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.3.3–5.3.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q19 May the controller access deleted queue memory or post completions for its old commands?
Follow the explanation
Establish the memory-reclamation boundary and distinguish an earlier write observed late from a new write after successful deletion.
1. Mechanism and scope
Deleting an SQ does not delete its shared CQ; already posted completions may remain for host consumption.
Track deleted QID, associated CQID, PRP-list address and memory lifetime. Reused addresses require distinguishing queue lifetimes.
2. Understand it through actions and results
Use successful Delete completion on Admin CQ as the boundary, not submission time or a host timeout.
Stop submissions, successfully delete, then reclaim the corresponding queue/list memory. With SQ-only deletion, handle existing posted entries in the surviving CQ.
After successful Delete SQ, no new completions for its old commands may be posted. Successful Delete CQ permits releasing its list; a deleted queue is no longer a valid DMA target.
- DMA
- Direct Memory Access, device access to memory
3. Avoid a misleading conclusion
Failure or absence of Delete completion does not authorize memory reclamation. Timeout is not a substitute for success.
Correlate write time, phase, Delete completion and host consumption. Late consumption of an old CQE is not necessarily a prohibited late write.
Sources: Base 2.4 §5.3.3–5.3.4 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.3.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.3.3–5.3.4 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §3.3.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q20 What is the scope of Queue Level Reset, and how is outstanding work handled?
Follow the explanation
Rebuild I/O queues without resetting the whole controller. PCIe Queue Level Reset means deletion and recreation, not a separate reset opcode.
1. Prepare the operation
Reset the target and its necessary dependencies. Rebuilding a CQ requires deleting its SQs first and recreating them afterward.
Use existing queue associations and Create/Delete rules, not a separate Queue Reset feature.
Use Delete SQ/CQ and Create CQ/SQ. QIDs may be reused, but memory and pointers begin a new lifetime.
2. Sequence and completion conditions
Normally let work finish before deletion. For cancellation, apply explicit/implicit Delete SQ completion rules. Initialize new CQ phases and create CQ before SQ.
New commands execute after reconstruction; old outstanding commands are not automatically migrated into the new SQ.
3. Handle unmet conditions
Deleting a referenced CQ returns 1/0Ch; premature SQ creation returns the applicable CQID error. Queue reset has no additional universal status.
Check teardown/recreation ordering, command-lifetime tracking and continued operation of independent queues.
Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.3.3–5.3.4 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.3.3–5.3.4 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q21 Are old I/O queues valid after Controller Reset, and what must the host do again?
Follow the explanation
Separate pre-failure commands from new work after recovery to avoid accepting stale completions.
1. Prepare the operation
Controller Level Reset deletes all I/O SQs/CQs of that controller, unlike deleting only one SQ.
Re-read necessary Identify data and verify queue allocations, entry sizes and interrupt settings rather than assuming previous values remain usable.
Admin registers, CC, Get/Set Features and Create CQ/SQ together establish the recovery path.
2. Sequence and completion conditions
For example, confirm RDY=0, initialize Admin CQ phases and CC, enable and wait for readiness, then restore needed features. Base 2.4 recommends Set Features Number of Queues during initialization; this example follows it and creates the CQ before the SQ. Submit new I/O only after its queue is created successfully.
Each new queue becomes valid after its successful Create completion on Admin CQ, even when reusing an identifier or address.
3. Handle unmet conditions
Updating old queue doorbells is not a valid recovery method. Failures of reconstruction commands follow their specific status rules.
Track queue lifetimes and command mappings across reset in host software; this is not a new NVMe wire field.
Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §3.5.1 · Base 2.4 §5.2.30.1.5 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §3.5.1 · Base 2.4 §5.2.30.1.5 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations and existing figure guides
Base printed page = PDF page−26; the other two use identical numbers. Locations follow the supplied PDF body and retain figure numbers. Shared pages contribute only the relevant definitions, excluding Fabrics and PCIe link/packet content.
- Base 2.4 · §3.1.4 (CAP, VS)
Printed pages 54–59 · PDF 80–85 · Figure 36–37 - Base 2.4 · §3.1.4 (AQA, ASQ, ACQ, CMBLOC)
Printed pages 66–68 · PDF 92–94 · Figure 44–47 - Base 2.4 · §3.3.1
Printed pages 88–91 · PDF 114–117 · Figure 73–74 - Base 2.4 · §3.3.3–3.4.1
Printed pages 101 · PDF 127 - Base 2.4 · §3.5.1
Printed pages 105–106 · PDF 131–132 - Base 2.4 · §3.7.1–3.7.4
Printed pages 120–124 · PDF 146–150 - Base 2.4 · §4.2.1, 4.2.3–4.2.4
Printed pages 144–157 · PDF 170–183 · Figure 97–105, 109 - Base 2.4 · §4.2.3
Printed pages 145–155 · PDF 171–181 · Figure 101–105 - Base 2.4 · §4.4
Printed pages 166–169 · PDF 192–195 · Figure 126–127 - Base 2.4 · §5.2.2
Printed pages 183–190 · PDF 209–216 · Figure 150–156 - Base 2.4 · §5.2.13.1.2
Printed pages 218–220 · PDF 244–246 · Figure 212 - Base 2.4 · §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Printed pages 244–256, 258, 262–264 · PDF 270–282, 284, 288–290 · Figure 232–244, 246, 252–253 - Base 2.4 · §5.2.13.1.18
Printed pages 276–278 · PDF 302–304 · Figure 270–271 - Base 2.4 · §5.2.30.1 (common fields, scope and persistence)
Printed pages 456–460 · PDF 482–486 · Figure 463–466 - Base 2.4 · §5.2.30.1.5
Printed pages 465–466 · PDF 491–492 · Figure 472–473 - Base 2.4 · §5.3.1–5.3.2
Printed pages 527–531 · PDF 553–557 · Figure 571–579 - Base 2.4 · §5.3.3–5.3.4
Printed pages 531–532 · PDF 557–558 · Figure 580–583 - Base 2.4 · §9.1–9.6.1
Printed pages 825–826 · PDF 851–852 - PCIe Transport 1.4 · §3.1–3.4
Printed pages 9–13 · PDF 9–13 · Figure 3–8 - PCIe Transport 1.4 · §3.5
Printed pages 13–16 · PDF 13–16 · Figure 9
When you need a field guide
Existing figure explanations have canonical locations; use these links instead of duplicating the same guide.
- Base 2.4 Figure 101 · Completion Queue Entry: Status Field
- Base 2.4 Figure 104 · Status Code – Command Specific Status Values
- Base 2.4 Figure 36 · Offset 0h: CAP – Controller Capabilities
- Base 2.4 Figure 44 · Offset 24h: AQA – Admin Queue Attributes
- Base 2.4 Figure 45 · Offset 28h: ASQ – Admin Submission Queue Base Address
- Base 2.4 Figure 46 · Offset 30h: ACQ – Admin Completion Queue Base Address
- Base 2.4 Figure 473 · Number of Queues – Completion Queue Entry Dword 0
- Base 2.4 Figure 97 · Common Completion Queue Entry Layout – Admin and All I/O Command Sets
Original documents used
- NVM Express Base Specification · Revision 2.4 · 2026-07-31
NVM-Express-Base-Specification-Revision-2.4-Ratified-2026.07.31.pdf - NVM Express NVM Command Set Specification · Revision 1.3 · 2026-07-31
NVM-Express-NVM-Command-Set-Specification-Revision-1.3-Ratified-2026.07.31.pdf - NVM Express NVMe over PCIe Transport Specification · Revision 1.4 · 2026-07-31
NVM-Express-NVMe-over-PCIe-Transport-Specification-Revision-1.4-Ratified-2026.07.31.pdf


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