NVMe Self-Study Bank: Error status and Error Information

NVMe · Q1–328

NVM Express Base 2.4NVM Command Set 1.3NVMe over PCIe Transport 1.4

Q93–Q106

Error status and Error Information

Start with one failed command, classify it and correlate completion with supplemental records and recovery evidence.

Each question is followed by its explanation. Start with the volume overview, then follow the field interpretations, comparisons or processes. Essential conditions and the normal path are visible from the start. All numerical examples are hypothetical. Status is written SCT/SC; h indicates hexadecimal.

SCT
Status Code Type

Three different kinds of evidence

Establish command identity before comparing records.

EvidenceWhat it establishesWhat it does not prove
CQECommand completion resultAll media effects were undone
Error InformationAdditional failure detailOne entry for every failed command
PELSupported persistent eventsA complete command trace
CQE
Completion Queue Entry

Worked interpretation: A request with both bad NSID and PRP may expose either fault first. Isolate NSID to test its required status.

NSID
Namespace Identifier
PRP
Physical Region Page, a data-page pointer

Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding)

Review the terminology when needed
Controller / namespace
A controller receives commands and manages access. A namespace is a logical storage space that commands can address. An NVM subsystem contains controllers and nonvolatile storage resources.
SQ / CQ / SQE / CQE
Submission and Completion Queues carry command entries (SQEs) and completion entries (CQEs). QID identifies a queue, CID distinguishes outstanding commands in one SQ, and NSID identifies a namespace.
Register / Identify / Feature / Log
A register exposes control or state. Identify queries capabilities and attributes; features query or configure operation; log pages report specific state or records. FID, LID, CNS and CSI select features, logs, Identify structures and command sets.
index / offset / zero-based
An index selects an entry, usually starting at 0; an offset measures distance from an origin in specified units. A zero-based count encodes count−1, but not every zero-valued field is a count. A Dword is 4 bytes; a byte is 8 bits.
Scope / reset / retention
Scope names the affected objects; retention means preserving state. Controller Reset (clearing CC.EN) is one form of Controller Level Reset, or CLR. Different CLR triggers can retain different registers.

Questions in this volume

  1. Q93 · How do opcode, field, CID and sequence errors differ?
  2. Q94 · How are namespace, log, queue, size and vector errors located?
  3. Q95 · Why must firmware, format and capacity errors be tied to their commands?
  4. Q96 · How do transfer, internal and namespace-readiness errors differ?
  5. Q97 · How do power loss, abort, SQ deletion and fused failures appear?
  6. Q98 · How do status, More, DNR and CRD guide recovery?
  7. Q99 · Which errors require Error Information?
  8. Q100 · How is an error entry correlated with its command and parameter?
  9. Q101 · Must an error entry match every CQE status bit?
  10. Q102 · How do concurrent errors, log capacity and Error Count interact?
  11. Q103 · Is a non-success CQE without a new error entry always nonconforming?
  12. Q104 · Can other commands continue after an ordinary command error?
  13. Q105 · When may serious failures set CFS, and how should the host interpret it?
  14. Q106 · How are CQEs, Error Information and persistent events correlated?

Q93 How do opcode, field, CID and sequence errors differ?

CID
Command Identifier, unique among outstanding commands in one SQ
Follow the explanation

Classify the failure before changing command encoding or host bookkeeping. An unsupported opcode differs from reusing an outstanding CID in the same SQ.

SQ
Submission Queue

1. What differs

Status describes the identified command. A parameter error does not establish queue-wide or controller-wide failure.

For SCT=0, SC 01h is Invalid Command Opcode, 02h Invalid Field, 03h CID Conflict and 0Ch Command Sequence Error. CID uniqueness applies to outstanding commands within one SQ.

SQ
Submission Queue

2. How to choose and verify

Check opcode support using Identify and Commands Supported and Effects, then command fields and sequence requirements. CID reuse requires the host outstanding list.

Preserve the SQE, establish command set and support, inspect fields, then reconstruct sequencing. Change one identified defect at a time.

SQE
Submission Queue Entry

A valid, successfully executed command returns success; a negative test passes by returning the applicable error, not by succeeding.

3. Conditions that shape the comparison

Use Invalid Field unless a more specific status is specified. For multiple simultaneous faults, status selection is vendor-defined unless priority is specified; CID-conflict search depth is implementation-specific.

Correlate support, SQE and CQE. A command with both an invalid opcode and invalid NSID does not isolate an exact-status test.

SQE
Submission Queue Entry

Sources: Base 2.4 §4.2.3 · Base 2.4 §4.1.1 · Base 2.4 §3.4.1–3.4.5 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q94 How are namespace, log, queue, size and vector errors located?

Follow the explanation

These errors concern different identified objects. Determine what the command addresses before testing existence, range and applicability.

1. What differs

NSID, LID and QID identify different objects; QSIZE encodes depth and IV selects a vector. Their numerical ranges are unrelated.

LID
Log Page Identifier

Typical SCT/SC pairs are namespace 0/0Bh, log 1/09h, queue ID 1/01h, queue size 1/02h and vector 1/08h. Invalid CQID in Create SQ uses Completion Queue Invalid 1/00h.

CQID
Completion Queue Identifier

2. How to choose and verify

Snapshot namespace lists, Supported Log Pages, CAP.MQES, Number of Queues and available interrupt resources.

Start with a valid command and alter only the tested field. A size test should keep QID, address and vector valid.

Only successful creation establishes a queue. After a negative test, ensure no usable partial queue configuration was left behind.

3. Conditions that shape the comparison

Apply codes to their defined commands and conditions. An inappropriate NSID in Get Log may require Invalid Field under the log-scope rules, not universally Invalid Namespace.

Compare the command-specific completion definition with the configuration at submission time.

Sources: Base 2.4 §4.2.3 · Base 2.4 §5.3.1–5.3.2 · Base 2.4 §5.3.3–5.3.4 · Base 2.4 §5.2.13–5.2.13.1.1 · Base 2.4 §3.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q95 Why must firmware, format and capacity errors be tied to their commands?

Follow the explanation

Distinguish image, format and resource problems. Correcting a firmware slot cannot fix insufficient namespace allocation capacity.

1. What differs

Firmware Commit concerns images and activation; Format concerns namespace format; Namespace and Capacity Management manage different resource levels.

Codes are firmware slot 1/06h, image 1/07h and format 1/0Ah. Namespace Insufficient Capacity is 1/15h, Capacity Management Insufficient Capacity 1/26h and generic Capacity Exceeded 0/81h.

2. How to choose and verify

Check FRMW, Firmware Slot Information, supported LBA formats, total/unallocated capacity and command scope.

LBA
Logical Block Address

Identify the opcode and its error conditions, then calculate requested bytes, logical blocks or allocation units consistently.

Positive tests establish the operation’s completion; negative tests establish rejection and the command-defined disposition of existing configuration.

3. Conditions that shape the comparison

These capacity codes are not interchangeable. Firmware Activation Requires Reset can indicate an additional activation step rather than an invalid image.

Compare pre/post Identify and logs and retain SCT with SC; SC alone loses its category.

Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.14.2.1 · Base 2.4 §5.2.24–5.2.25, 8.1.17 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q96 How do transfer, internal and namespace-readiness errors differ?

Follow the explanation

These identify data movement, internal processing and namespace accessibility, requiring different recovery actions.

1. What differs

Transfer/internal errors describe a command; readiness concerns the selected namespace. None alone proves destruction of all namespaces.

Codes are 0/04h, 0/06h and 0/82h. Admin Command Media Not Ready, 0/24h, has separate CRIME and timing conditions.

2. How to choose and verify

Preserve pointers, host memory mappings, CSTS and namespace state; read Error Information when applicable. Ready mode and CFS provide distinct evidence.

Preserve the CQE, check buffer addresses and lifetime, then logs, CSTS and namespace state. Do not treat failed-read data as a valid result.

A successful command after recovery establishes its result; RDY=1 alone does not establish immediate access to every namespace.

3. Conditions that shape the comparison

Namespace Not Ready does not replace defined ANA statuses. Internal Error does not universally require CFS=1.

Valid pointers do not rule out internal errors, and temporary namespace unavailability does not imply an unsupported opcode.

4. Asynchronous Event notification conditions

Internal Error details should be reported through an appropriate error AER; transfer or readiness errors do not universally require that same event. Distinguish occurrence, reporting conditions and available requests.

Sources: Base 2.4 §4.2.3 · Base 2.4 §9.1–9.6.1 · Base 2.4 §3.5.3–3.5.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q97 How do power loss, abort, SQ deletion and fused failures appear?

Follow the explanation

Abort cause determines status and whether a completion can be expected. Sudden power loss or reset can remove the completion channel.

1. Distinguish the failure conditions

Abort targets one command, SQ deletion covers its outstanding commands and fused failure affects the pair; power and reset can have broader scope.

Target-command codes are power-loss notification 0/05h, abort requested 0/07h, SQ deletion 0/08h, failed fused 0/09h and missing fused 0/0Ah.

A power-loss-notification status does not mean every power removal produces CQEs. A missing fused partner differs from a partner that failed.

2. Establish the cause from evidence

Preserve target IDs, Abort/Delete completions, CC/CSTS and FUSE encoding to reconstruct the cause.

Establish queue validity before consuming target completions. After reset, rebuild queues and tracking; handle Abort and target CQEs separately.

3. Outcome and follow-up checks

Correct cancellation does not require target success. Verify one target completion, or abandon old completion expectations under reset rules.

Correlate target, management completions and queue/power transitions by time rather than using one final status for the entire sequence.

First distinguish an actual power-loss notification from abrupt loss of power, since completion expectations differ.

Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.1 · Base 2.4 §5.3.3–5.3.4 · Base 2.4 §3.4.1–3.4.5 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q98 How do status, More, DNR and CRD guide recovery?

DNR
Do Not Retry, a completion retry indication
Follow the explanation

Diagnose before retrying. DNR=0 permits the possibility of success, not unlimited immediate retries or assumptions about partial effects.

DNR
Do Not Retry, a completion retry indication

1. Preserve the evidence first

These fields describe one completion; Abort, queue deletion and reset have broader scopes and depend on failure severity and channel availability.

Use SCT/SC, M, DNR and CRD with ACRE and CRDT1–3; M=1 points to additional Error Information.

With ACRE=1 and DNR=0, CRD selects CRDT1–3 or zero extra delay. CRD is reserved when DNR=1 or ACRE=0.

2. Work through the possible causes

First check whether the test incorrectly interprets DNR=0 as a guarantee of immediate retry success.

Decode the error and additional information, correct parameters or wait for state, then assess retry safety. Recover queues or the controller when their channels are compromised.

3. Connect observations to specification conditions

Successful recovery needs a valid new result and control over old-command effects; retry success alone does not rule out duplicate writes.

Command Interrupted 0/21h requires ACRE=1 and DNR=0. Format In Progress also requires DNR=0; other names do not establish a universal DNR value.

Compare retry timing with CRD/CRDT. Waiting at least the indicated delay is recommended, but an earlier retry is not itself an error.

Sources: Base 2.4 §4.2.3 · Base 2.4 §5.2.30.1.15 · Base 2.4 §5.2.14.2.1 · Base 2.4 §9.1–9.6.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q99 Which errors require Error Information?

Follow the explanation

Error Information extends CQEs and can describe non-command errors; it is not a mandatory transaction ledger of every failed command.

1. Mechanism and scope

LID 01h is controller-wide; SQID/CID validity determines whether an entry is command-specific.

LID
Log Page Identifier
SQID
Submission Queue Identifier

Read LID 01h and retain ECNT, SQID, CID, STS, Parameter Error Location, NSID and LPVER.

2. Understand it through actions and results

ELPE determines entry capacity; CQE.M identifies additional command information, and error AERs can also lead to this log.

After an error with M=1, promptly preserve enough entries rather than assuming the newest entry is the target.

Success is a correlated explanatory entry; SQID/CID=FFFFh can be correct for a non-command-specific error.

3. Avoid a misleading conclusion

M=0 does not mandate an entry for every Invalid Field. For M=1 with missing information, exclude overwrite, reset clearing and querying the wrong controller.

Validate correlation among M, error AERs and entries rather than requiring failure count to equal entry count.

4. Evidence supplied by the log

A successful CQE does not require a new Error Information entry. Read the complete conditions in this volume

Sources: Base 2.4 §5.2.13.1.2 · Base 2.4 §4.2.3 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q100 How is an error entry correlated with its command and parameter?

Follow the explanation

Correlation turns a reported parameter fault into inspectable original bytes; a status name alone rarely locates the actual encoding mistake.

1. Establish the source and scope

SQID+CID identifies a command within one queue lifetime; reuse requires ECNT, timing and a submission snapshot.

Check LPVER, which is 1 in Base 2.4; CSI/OPC are valid for LPVER≥1.

CSI
Command Set Identifier

2. Fields, units and worked interpretation

Parameter Error Location bits 7:0 give SQE byte offset and bits 10:8 the bit within it; multi-bit/byte fields use their least-significant position. This PEL abbreviation differs from Persistent Event Log.

Establish queue lifetime, match IDs/opcode/namespace, then decode the original SQE at the reported byte and bit.

A successful correlation identifies the submitted value and violated condition, enabling a one-field correction test.

3. Conditions that change the interpretation

Non-command-specific errors use FFFFh for SQID, CID and Parameter Error Location; do not use it as a command-memory offset.

Interpret LBA/CSINFO only after identifying namespace and command set; not every error carries a failing LBA.

LBA
Logical Block Address

Sources: Base 2.4 §5.2.13.1.2 · Base 2.4 §4.1.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q101 Must an error entry match every CQE status bit?

Follow the explanation

Separate command status from phase; comparing the entire word can reject a valid entry.

1. What differs

Compare matched command-specific records; non-command errors have no originating CQE for exact comparison.

Error STS bits 15:1 contain command status; bit 0 may indicate the CQE phase. Normalize their different placements before comparison.

2. How to choose and verify

Decode Figure 212 STS and Figure 101 status rather than assuming an OS-transformed numeric representation.

Preserve raw data, extract status components and handle phase separately, confirming ECNT and command IDs.

Matched command status should agree; phase follows its optional-reporting definition rather than requiring identical raw words.

3. Conditions that shape the comparison

Non-command errors use the most applicable status; absence of a CQE is not itself a defect. For multiple faults compare the selected completion status.

Check decoder shifts for SC, SCT and phase; a parser defect can make every entry appear inconsistent.

Sources: Base 2.4 §5.2.13.1.2 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q102 How do concurrent errors, log capacity and Error Count interact?

Follow the explanation

Error Count identifies records while capacity limits visible history; a small log can contain large cumulative identifiers.

1. Mechanism and scope

Capacity and ordering are per-controller Error Information, not separate identical arrays for every namespace.

ECNT is 64-bit and begins at one; zero marks an invalid entry. Incrementing the maximum wraps to one, not zero.

2. Understand it through actions and results

ELPE is zero-based: ELPE=3 means at most four 64-byte entries.

Read newest first. When full, the controller should insert the new entry and discard the oldest; retain ECNT across samples to detect updates.

With capacity four and latest count nine, entries 9,8,7,6 can be visible; absence of 1–5 does not mean they never occurred.

3. Avoid a misleading conclusion

Zero is not a zeroth error. Gaps require considering updates and removed records before diagnosing corruption.

Distinguish the SMART cumulative entry count from current log occupancy; they need not be equal.

Sources: Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.14.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q103 Is a non-success CQE without a new error entry always nonconforming?

Follow the explanation

This tests sufficiency of evidence: command failure and required additional error information are separate requirements.

1. Mechanism and scope

Evaluate this command and its logging conditions; an unrelated new entry does not satisfy its evidence requirement.

More is central: M=1 identifies additional information for this command. Error AERs and particular command rules may impose further requirements.

2. Understand it through actions and results

Preserve M, SCT/SC, ECNT before/after, ELPE and reset timing.

Establish the logging requirement, exclude wrong controller, short read, overwrite and reset clearing, then evaluate missing required information.

A valid result may be that no entry is required or that required information exists. Compliance does not require every failure to increment Error Count.

3. Avoid a misleading conclusion

Unexplained missing information for M=1 is a concrete inconsistency; M=0 without an additional rule does not establish the same defect.

Attach the requirement, original CQE and log snapshots rather than only stating that no entry was seen.

4. Evidence supplied by the log

A successful CQE does not require a new Error Information entry. Read the complete conditions in this volume

Sources: Base 2.4 §5.2.13.1.2 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q104 Can other commands continue after an ordinary command error?

Follow the explanation

Most command errors do not compromise queues, so recovery can remain local instead of aborting unrelated work.

1. Mechanism and scope

Distinguish command, queue and controller failures, widening recovery only with broader evidence.

Base 9.1 recommends continued processing for most command errors and queue recreation for serious queue failures.

2. Understand it through actions and results

Inspect CQEs, CFS, queue pointers and continued completion of other commands, with Error Information for context.

Preserve the failed command and continue valid work if queues remain sound; stop and recover damaged queues in dependency order.

Later valid commands can succeed while the earlier failure remains a distinct result.

3. Avoid a misleading conclusion

Serious Admin-channel failure or an uncompleted queue deletion calls for Controller Level Reset, unlike ordinary Invalid Field.

Observe commands in the same SQ, shared CQ and other CQs to distinguish congestion from a global processing stop.

CQ
Completion Queue

Sources: Base 2.4 §9.1–9.6.1 · Base 2.4 §4.2.3 · Base 2.4 §5.3.3–5.3.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q105 When may serious failures set CFS, and how should the host interpret it?

Follow the explanation

CFS exposes a serious condition when completion communication may fail; it is not a mandatory flag for every command error.

1. Preserve the evidence first

CFS is controller state; impact on other controllers requires separate evidence.

Read CFS directly and preserve CC, CAP, readiness and timing; for secondary controllers also check Online/Offline state.

Base 9.5 permits CFS for serious conditions preventing CQE communication. Offline secondary controllers have a separate virtualization use of CFS.

2. Work through the possible causes

First determine whether this is an Offline secondary controller rather than a hardware failure.

On timeouts or repeated errors, read CFS. For a fatal condition, reset/reinitialize that controller, then consider supported platform-appropriate subsystem reset if the condition persists.

3. Connect observations to specification conditions

Recovery must restore usable state and command processing; CFS clearing does not replace queue and readiness initialization.

CFS is not a CQE and its condition is not signaled by an interrupt. Lost completion communication cannot support a requirement for every outstanding command to return Internal Error.

Correlate role, virtualization state, communication and reset outcome to distinguish expected Offline state from fatal failure.

4. Whether CQE, DNR and More apply here

Reading CFS has no CQE, so DNR/More do not apply to the register read; decode them only in a separately received completion.

Sources: Base 2.4 §9.1–9.6.1 · Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §8.2.7 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q106 How are CQEs, Error Information and persistent events correlated?

Follow the explanation

CQEs describe commands, Error Information extends errors and PEL records significant events. Correlation adds evidence without requiring one-to-one records.

1. Preserve the evidence first

Establish controller, namespace, queue lifetime and event scope; related scopes do not necessarily identify one command.

Check ELPE, PEL support/event bitmap and timestamp origin/synchronization.

Use SQID/CID/status, then ECNT/NSID/opcode, then PEL event type/controller/time/data. Parameter Error Location is not a PEL file offset.

2. Work through the possible causes

First align sampling times and controller identity before interpreting apparent contradictions.

Match command and error entry first, then related PEL events; account for timestamp changes before ordering events.

3. Connect observations to specification conditions

A useful result states what each source establishes and leaves unresolved; Format Start does not establish Format Completion.

A missing PEL entry is not automatically a defect; check support and recording conditions, but optional support does not excuse required behavior once advertised.

Correlate capability, trigger, CQE and retention on one timeline; entries clearing and counters persisting after reset can both be correct.

Sources: Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §5.2.30.1.8 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.2

Back to questions

Shared rules linked from the answers

Each shared mechanism is explained in full once in this volume. Use browser Back to return to the question; explicit command or feature exceptions take precedence.

Command completion, events and records · Are Error Information or other logs updated?

A successful CQE does not require a new Error Information entry. For an error with More=1, read LID 01h and correlate SQID, CID and Error Count; not every unsuccessful CQE requires a new entry. Re-read the interfaces named in this question for the state the operation changes.

Source locations and existing figure guides

Base printed page = PDF page−26; the other two use identical numbers. Locations follow the supplied PDF body and retain figure numbers. Shared pages contribute only the relevant definitions, excluding Fabrics and PCIe link/packet content.

  • Base 2.4 · §3.1.4 (CC, CSTS, NSSR)
    Printed pages 60–66 · PDF 86–92 · Figure 41–43
  • Base 2.4 · §3.2.1
    Printed pages 78–81 · PDF 104–107
  • Base 2.4 · §3.4.1–3.4.5
    Printed pages 101–105 · PDF 127–131 · Figure 80–81
  • Base 2.4 · §3.5.3–3.5.4
    Printed pages 109–113 · PDF 135–139 · Figure 84–85
  • Base 2.4 · §3.7.1–3.7.4
    Printed pages 120–124 · PDF 146–150
  • Base 2.4 · §4.1.1
    Printed pages 139–142 · PDF 165–168 · Figure 92–93
  • Base 2.4 · §4.2.1, 4.2.3–4.2.4
    Printed pages 144–157 · PDF 170–183 · Figure 97–105, 109
  • Base 2.4 · §4.2.3
    Printed pages 145–155 · PDF 171–181 · Figure 101–105
  • Base 2.4 · §5.2.1
    Printed pages 181–182 · PDF 207–208 · Figure 147–149
  • Base 2.4 · §5.2.2
    Printed pages 183–190 · PDF 209–216 · Figure 150–156
  • Base 2.4 · §5.2.2 (PCIe-applicable events)
    Printed pages 183–191 · PDF 209–217 · Figure 150–160
  • Base 2.4 · §5.2.13–5.2.13.1.1
    Printed pages 212–218 · PDF 238–244 · Figure 203–211
  • Base 2.4 · §5.2.13.1.2
    Printed pages 218–220 · PDF 244–246 · Figure 212
  • Base 2.4 · §5.2.13.1.14 (header, reset, hardware, Set Feature events)
    Printed pages 244–256, 258, 262–264 · PDF 270–282, 284, 288–290 · Figure 232–244, 246, 252–253
  • Base 2.4 · §5.2.13.1.14–5.2.13.1.14.2.5 (exclude PCIe link/packet decoding)
    Printed pages 244–256, 258 · PDF 270–282, 284 · Figure 232–244, 246
  • Base 2.4 · §5.2.14.2.1
    Printed pages 340–387 · PDF 366–413 · Figure 338–341
  • Base 2.4 · §5.2.24–5.2.25, 8.1.17
    Printed pages 442–448, 660–664 · PDF 468–474, 686–690 · Figure 442–450
  • Base 2.4 · §5.2.30.1.8
    Printed pages 469–471 · PDF 495–497 · Figure 479–480
  • Base 2.4 · §5.2.30.1.15
    Printed pages 475–477 · PDF 501–503 · Figure 491
  • Base 2.4 · §5.3.1–5.3.2
    Printed pages 527–531 · PDF 553–557 · Figure 571–579
  • Base 2.4 · §5.3.3–5.3.4
    Printed pages 531–532 · PDF 557–558 · Figure 580–583
  • Base 2.4 · §8.2.7
    Printed pages 754–758 · PDF 780–784 · Figure 796
  • Base 2.4 · §9.1–9.6.1
    Printed pages 825–826 · PDF 851–852

When you need a field guide

Existing figure explanations have canonical locations; use these links instead of duplicating the same guide.

Original documents used
  • NVM Express Base Specification · Revision 2.4 · 2026-07-31
    NVM-Express-Base-Specification-Revision-2.4-Ratified-2026.07.31.pdf
  • NVM Express NVM Command Set Specification · Revision 1.3 · 2026-07-31
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  • NVM Express NVMe over PCIe Transport Specification · Revision 1.4 · 2026-07-31
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