NVMe Self-Study Bank: Controller initialization and disable

NVMe · Q1–328

NVM Express Base 2.4NVM Command Set 1.3NVMe over PCIe Transport 1.4

Q1–Q9

Controller initialization and disable

Understand controller state transitions before commands. Discovering capabilities is not enabling; setting EN is not readiness; RDY=1 need not establish readiness of every media operation. This volume connects timing, state and permitted actions.

Each question is followed by its explanation. Start with the volume overview, then follow the field interpretations, comparisons or processes. Essential conditions and the normal path are visible from the start. All numerical examples are hypothetical. Status is written SCT/SC; h indicates hexadecimal.

SCT
Status Code Type

From disabled to command submission

Wait for the previous lifetime to end before configuring the next; both waits require RDY, not merely the EN value written by the host.

StageObservation or actionCondition for advancing
Disable completeCC.EN=0; CSTS.RDY=0Configure AQA, ASQ, ACQ and CC
EnablingEN 0→1 starts the timerWait for RDY=1; check CFS and applicable timeout
Interface readyRDY=1; apply media restrictions for the ready modeSubmit permitted Admin commands, then create I/O queues
Disabling againEN 1→0; stop new submissionsWait for RDY=0 before another lifetime

Worked interpretation: With hypothetical CAP.TO=4, the disable timeout is 4×500 ms=2 s. This is not an I/O command timeout. Enable additionally requires CAP.CRMS and the selected CRTO rules; 2 s is not universal.

Sources: Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §3.1.4 (CRTO) · Base 2.4 §3.5.1 · Base 2.4 §3.5.3–3.5.4

Review the terminology when needed
Controller / namespace
A controller receives commands and manages access. A namespace is a logical storage space that commands can address. An NVM subsystem contains controllers and nonvolatile storage resources.
SQ / CQ / SQE / CQE
Submission and Completion Queues carry command entries (SQEs) and completion entries (CQEs). QID identifies a queue, CID distinguishes outstanding commands in one SQ, and NSID identifies a namespace.
Register / Identify / Feature / Log
A register exposes control or state. Identify queries capabilities and attributes; features query or configure operation; log pages report specific state or records. FID, LID, CNS and CSI select features, logs, Identify structures and command sets.
index / offset / zero-based
An index selects an entry, usually starting at 0; an offset measures distance from an origin in specified units. A zero-based count encodes count−1, but not every zero-valued field is a count. A Dword is 4 bytes; a byte is 8 bits.
Scope / reset / retention
Scope names the affected objects; retention means preserving state. Controller Reset (clearing CC.EN) is one form of Controller Level Reset, or CLR. Different CLR triggers can retain different registers.

Questions in this volume

  1. Q01 · How does a host discover version, queue limits, timeouts, doorbell stride, page sizes and command sets from CAP and VS?
  2. Q02 · In what order are AQA, ASQ, ACQ and CC programmed, and what happens if they are wrong?
  3. Q03 · How does a host judge enable completion using CC.EN, CSTS.RDY and the timeout fields?
  4. Q04 · How is disable completion detected, and may the host re-enable before it completes?
  5. Q05 · May a host submit commands or update doorbells while CSTS.RDY is zero?
  6. Q06 · What does CSTS.CFS mean, and how should the host recover from initialization failure or a fatal state?
  7. Q07 · Which ready modes exist, and how should the host handle limited readiness?
  8. Q08 · How do Enable, Disable, Controller Reset, NVM Subsystem Reset and Shutdown differ?
  9. Q09 · What must be reinitialized after Controller Reset?

Q01 How does a host discover version, queue limits, timeouts, doorbell stride, page sizes and command sets from CAP and VS?

Follow the explanation

Discover legal interface configurations before issuing commands. CAP advertises capabilities; CC contains host selections. Capability bits are not values to copy blindly into configuration fields.

1. Establish the source and scope

These reads observe one controller without changing queues or media. A version number does not establish support for every optional feature.

VS.MJR/MNR/TER encode the version. CAP.MQES+1 limits I/O queue entries, CQR specifies physical-contiguity requirements, and CSS describes command-set support.

2. Fields, units and worked interpretation

CAP.TO uses 500 ms units. Doorbell stride is 2^(2+DSTRD) bytes; supported pages range from 2^(12+MPSMIN) to 2^(12+MPSMAX) bytes. Enable timeout also requires CRTO.

Map the NVMe registers, read VS/CAP, select legal MPS/CSS/AMS and ready mode, then configure queues. If IOCSS=1, discover combinations with Identify CNS 1Ch after enabling.

CNS
Controller or Namespace Structure, selecting Identify data

The result is configuration information, not a CQE. For example, MQES=03FFh means up to 1024 slots; DSTRD=2 means adjacent doorbells are 16 bytes apart.

CQE
Completion Queue Entry

3. Conditions that change the interpretation

Reading read-only registers has no Invalid Field CQE. Later programming unsupported CC.MPS/AMS values can be undefined behavior, not a condition with a guaranteed error completion.

CQE
Completion Queue Entry

Cross-check CAP.CSS against CC.CSS and Identify combinations, and MQES against Create Queue QSIZE. Admin queues have their separate 4096-slot AQA limit.

Sources: Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.1.4 (CRTO) · Base 2.4 §3.5.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1

Back to questions

Q02 In what order are AQA, ASQ, ACQ and CC programmed, and what happens if they are wrong?

Follow the explanation

Provide valid Admin SQ/CQ storage before enabling the controller. Establish memory and pointers before allowing command processing.

SQ
Submission Queue
CQ
Completion Queue

1. Prepare the operation

This controls the controller's management interface. A wrong queue address may prevent every subsequent Identify or Get Features from completing.

Check CAP's MPS range, CSS, AMS and CRMS, together with AQA's Admin queue limits.

AQA.ASQS/ACQS encode entries−1. ASQ/ACQ contain physical bases aligned to CC.MPS. Configure CSS, MPS, AMS and CRIME in CC; NVM I/O uses IOSQES=6 and IOCQES=4.

2. Sequence and completion conditions

Wait for the previous reset to reach RDY=0. Allocate contiguous Admin queues and clear Admin CQ phases. Program AQA/ASQ/ACQ and legal CC fields with EN=0, then enable and wait for RDY=1. Set I/O entry sizes before Create I/O Queue.

CQ
Completion Queue

The Admin queues become usable for Identify. I/O queues are not automatically created, and independent mode does not imply that every medium is ready.

3. Handle unmet conditions

Enabling with an AQA size of zero, changing MPS while enabled or selecting unsupported MPS/AMS has undefined results. Do not invent Invalid Field CQEs for these register violations.

Validate register encodings and then a correctly identified Identify completion. CC.EN=1 alone does not establish successful initialization.

Sources: Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §3.5.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1

Back to questions

Q03 How does a host judge enable completion using CC.EN, CSTS.RDY and the timeout fields?

Follow the explanation

Separate the enable request from readiness and avoid premature recovery caused by a wrong timeout. Base 2.4 requires considering CRTO as well.

1. Prepare the operation

This establishes readiness of the target controller; media availability also depends on the selected ready mode.

Read CAP.CRMS, CC.CRIME, CRTO.CRWMT/CRIMT and CAP.TO. CAP.TO alone does not cover every enable timeout.

2. Sequence and completion conditions

The two readiness deadlines

Interface readiness and media readiness are separate. Both deadlines start at Enable; the media timer does not restart when RDY becomes 1.

  1. Start: CC.EN changes from 0 to 1

    Record the time and CC.CRIME; observe RDY and CFS throughout initialization.

  2. Branch A: With Media

    Use CRWMT for the readiness deadline, in 500 ms units. Submit commands permitted by this mode only after RDY=1.

  3. Branch B: Independent

    Use CRIMT for interface readiness and CRWMT for the media deadline. RDY=1 does not prove media health or availability; command-specific media conditions still apply.

  4. Check a single timeline

    With hypothetical CRIMT=2 and CRWMT=20, the deadlines are 1 s and 10 s after Enable.

A and B are alternative modes, not consecutive actions. Evaluate CFS and failure conditions; merely observing RDY=1 does not establish successful initialization.

3. Handle unmet conditions

Register enabling has no CQE. While media is unready, eligible commands may return Namespace Not Ready (SCT=0, SC=82h) or Admin Command Media Not Ready (0/24h).

SCT
Status Code Type

Correlate timing, CRIME, command type and status. Figure 84's eligible Admin commands and restrictions do not permit rejecting every Admin command temporarily.

4. Correlate error completions and records

Enabling has no DNR/More. Eligible media-not-ready responses may have DNR=0 during the allowed Independent-mode interval; that transient explanation cannot continue with DNR=0 beyond CRWMT. More reflects additional Error Information.

DNR
Do Not Retry, a completion retry indication

For an initialization-deadline failure meeting §3.5.4.1, a controller supporting PEL shall record an NVM Subsystem Hardware Error Event with Controller Ready Timeout Exceeded. This is not a record for every successful enable.

Sources: Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.1.4 (CRTO) · Base 2.4 §3.5.3–3.5.4 · Base 2.4 §3.5.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1

Back to questions

Q04 How is disable completion detected, and may the host re-enable before it completes?

Follow the explanation

Establish that old command processing has stopped before beginning another initialization lifetime.

1. Prepare the operation

Clearing EN resets this controller and all its I/O queues; it does not merely pause one SQ.

SQ
Submission Queue

CAP.TO defines the worst-case wait for RDY 1→0 after EN is cleared. Preserve CC/CSTS snapshots too.

In the normal enabled state, initiate EN 1→0 with RDY=1; RDY=0 indicates readiness to enable again.

2. Sequence and completion conditions

Stop new submissions, clear EN and poll RDY. Once zero, reinitialize Admin CQ and host tracking, configure CC and enable again.

RDY=0 establishes disable completion; receiving a CQE for every old command is not required. Old I/O queues are invalid.

3. Handle unmet conditions

Setting EN 0→1 while RDY remains 1 has undefined results. This is not an Admin request requiring Command Sequence Error.

Check EN/RDY transitions and retirement of old queues. Residual data in an old queue does not prove it is reusable.

Sources: Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1

Back to questions

Q05 May a host submit commands or update doorbells while CSTS.RDY is zero?

Follow the explanation

Distinguish preparing an SQE in host memory from submitting it. A doorbell is the submission boundary and cannot be used prematurely.

SQE
Submission Queue Entry

1. When commands may be submitted

This applies to Admin and I/O submission on this PCIe controller. Configuring Admin queue registers during initialization is different from command submission.

Check CSTS.RDY, CC.EN and queue existence. Even RDY=1 requires a created queue and consideration of shutdown state.

Wait for RDY=1 and a valid queue lifetime, make the SQE visible to the device, then update SQ Tail.

SQE
Submission Queue Entry

2. Doorbells do not replace readiness

SQ Tail announces submissions; CQ Head announces consumed completions. Neither is a command for making the controller ready.

Violating readiness or queue-lifetime preconditions has no guaranteed CQE. A disabled Admin Queue cannot be relied upon to report the misuse.

EN=1, RDY=0 and a timeout first indicate an initialization-state issue; an illegally early Identify is not evidence that Identify is unsupported.

Sources: Base 2.4 §3.3.3–3.4.1 · Base 2.4 §3.3.1 · Base 2.4 §3.1.4 (CC, CSTS, NSSR) · PCIe Transport 1.4 §3.1–3.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1

Back to questions

Q06 What does CSTS.CFS mean, and how should the host recover from initialization failure or a fatal state?

Follow the explanation

CFS normally signals a serious controller condition rather than an individual command error. A virtualized secondary controller also sets CFS when Offline, so establish its role and Online/Offline state before diagnosing a hardware failure.

1. Preserve the evidence first

The failure may affect controller-wide command service. CFS and an individual namespace media error are not interchangeable.

Observe CSTS.CFS with RDY, CC.EN and the applicable timeout. No Identify optional-capability bit permits ignoring CFS.

Preserve registers and available CQEs/logs first. Collect diagnostics if the Admin path still works, without waiting indefinitely for an inaccessible Get Log Page.

2. Work through the possible causes

First confirm valid register access and an actual CFS value of 1. An all-ones failed read is not evidence that every status bit is asserted.

Perform Controller Level Reset as appropriate to the failure and accessible interface, then reinitialize. An unresponsive interface requires platform recovery; a CC.EN reset is not guaranteed to repair every fault.

3. Connect observations to specification conditions

Verify RDY, Identify and command completion on new queues after recovery. Clearing CFS alone does not validate data integrity.

Internal Error (SCT=0, SC=06h) may apply when affected commands can still complete. Serious failure preventing CQE communication may set CFS; do not require a CQE for every command.

Correlate CFS, initialization deadlines and hardware records at the same time. One Invalid Field completion is not itself controller-fatal evidence.

Sources: Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §9.1–9.6.1 · Base 2.4 §3.5.3–3.5.4 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §8.2.7

Back to questions

Q07 Which ready modes exist, and how should the host handle limited readiness?

Follow the explanation

Allow management work before media initialization finishes while retaining an explicit media-readiness deadline.

1. Mechanism and scope

The modes are Controller Ready With Media and Controller Ready Independent of Media, not arbitrary degraded-ready encodings.

CRIME=0 selects With Media; CRIME=1 selects Independent. RDY, CRTO.CRIMT/CRWMT and Figure 84's command classes determine permitted work.

2. Understand it through actions and results

CAP.CRMS.CRWMS/CRIMS advertise support. With CAP.CRMS=11b, CC.CRIME selects the mode.

Select before enable. After Independent-mode RDY=1, perform media-independent discovery; defer eligible media operations based on transient status and track CRWMT from enable.

Normal With Media readiness includes required media readiness. Independent RDY=1 initially establishes interface and eligible-command readiness, not readiness of every namespace.

3. Avoid a misleading conclusion

Eligible cases may return 0/82h or 0/24h. The latter is restricted to appropriate Admin commands in Independent mode. Continuing the same transient DNR=0 explanation beyond the media deadline violates that timing rule.

Cross-check CAP support, CC selection, timeouts and behavior. CSTS.PP is a separate processing-pause indication, not a third ready mode.

Sources: Base 2.4 §3.5.3–3.5.4 · Base 2.4 §3.1.4 (CRTO) · Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1

Back to questions

Q08 How do Enable, Disable, Controller Reset, NVM Subsystem Reset and Shutdown differ?

Follow the explanation

Separate starting service, stopping/resetting and preparing for power removal. Reset is not a replacement for orderly shutdown.

1. What differs

Enable and CC.EN clearing target a controller. NVM Subsystem Reset covers its defined subsystem/domain scope. Shutdown also distinguishes controller and subsystem types.

Enable is EN 0→1; Controller Reset is EN 1→0. Writing 4E564D65h to supported NSSR.NSSRC requests subsystem reset. Normal controller shutdown uses CC.SHN=01b and waits for SHST=10b.

2. How to choose and verify

CAP.NSSRS advertises NSSR support; shutdown capability and CSTS.ST distinguish shutdown scope.

Coordinate I/O, notify shutdown and await completion before normal power removal. Select a suitable reset for recovery, then rebuild the operating environment.

Enable uses RDY=1; disable/reset uses its corresponding state; shutdown uses SHST=10b. Completed shutdown does not mean every register has its reset value.

3. Conditions that shape the comparison

Register operations have no common CQE. During shutdown, commands may return Commands Aborted due to Power Loss Notification (0/05h); that code is not universal for commands interrupted by reset.

Record the trigger and scope before comparing retained state. A log saying only “reset” cannot explain differences in AQA, PCIe state or features.

Sources: Base 2.4 §3.1.4 (CC, CSTS, NSSR) · Base 2.4 §3.6.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1

Back to questions

Q09 What must be reinitialized after Controller Reset?

Follow the explanation

Establish a fresh operating lifetime rather than reusing old pointers, phases and outstanding commands.

1. Identify the trigger and affected objects

Here Controller Reset specifically means clearing CC.EN. Do not mix in the register-retention rules of FLR or NVM Subsystem Reset.

FLR
Function Level Reset

Use §3.7.2's exceptions and register Reset columns; for features examine scope, saveability and Figures 126/127/466.

2. State changes and recovery

This reset preserves AQA/ASQ/ACQ, specified PMR registers and CMBMSC, but still resets Admin Queue pointers. All I/O queues are deleted and CC selections require reconfiguration. Saveable features restore Saved, or Default without Saved, under reset-scope rules; unsaveable features use their persistence rules. Reconfigure HMB.

PMR
Persistent Memory Region
HMB
Host Memory Buffer

Wait for RDY=0, verify retained Admin memory remains valid and initialize Admin CQ phases to zero. Configure and enable, rediscover needed capabilities/features, renegotiate Number of Queues, then create CQs before SQs.

New commands complete in the new queue lifetime. Reusing a QID or address does not resume the old queue.

3. Verify retention and recovery

There is no universal Reset Status owed for every old command. Invalid reconstruction parameters follow Create-command rules; writing doorbells for stale memory is not a recovery method.

Compare register values, Get Features and actual queue capability. Retention of AQA is distinct from validity of Admin CQ contents.

First check retirement of old outstanding tracking and phase reinitialization. A reused CID must not resolve to a command from the previous lifetime.

CID
Command Identifier, unique among outstanding commands in one SQ

Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.1.4 (AQA, ASQ, ACQ, CMBLOC) · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §9.1–9.6.1

Back to questions

Source locations and existing figure guides

Base printed page = PDF page−26; the other two use identical numbers. Locations follow the supplied PDF body and retain figure numbers. Shared pages contribute only the relevant definitions, excluding Fabrics and PCIe link/packet content.

  • Base 2.4 · §3.1.4 (CAP, VS)
    Printed pages 54–59 · PDF 80–85 · Figure 36–37
  • Base 2.4 · §3.1.4 (CC, CSTS, NSSR)
    Printed pages 60–66 · PDF 86–92 · Figure 41–43
  • Base 2.4 · §3.1.4 (AQA, ASQ, ACQ, CMBLOC)
    Printed pages 66–68 · PDF 92–94 · Figure 44–47
  • Base 2.4 · §3.1.4 (CRTO)
    Printed pages 72–73 · PDF 98–99 · Figure 57
  • Base 2.4 · §3.3.1
    Printed pages 88–91 · PDF 114–117 · Figure 73–74
  • Base 2.4 · §3.3.3–3.4.1
    Printed pages 101 · PDF 127
  • Base 2.4 · §3.5.1
    Printed pages 105–106 · PDF 131–132
  • Base 2.4 · §3.5.3–3.5.4
    Printed pages 109–113 · PDF 135–139 · Figure 84–85
  • Base 2.4 · §3.6.1
    Printed pages 114–115 · PDF 140–141
  • Base 2.4 · §3.7.1–3.7.4
    Printed pages 120–124 · PDF 146–150
  • Base 2.4 · §4.4
    Printed pages 166–169 · PDF 192–195 · Figure 126–127
  • Base 2.4 · §5.2.13.1.14 (header, reset, hardware, Set Feature events)
    Printed pages 244–256, 258, 262–264 · PDF 270–282, 284, 288–290 · Figure 232–244, 246, 252–253
  • Base 2.4 · §5.2.30.1 (common fields, scope and persistence)
    Printed pages 456–460 · PDF 482–486 · Figure 463–466
  • Base 2.4 · §8.2.7
    Printed pages 754–758 · PDF 780–784 · Figure 796
  • Base 2.4 · §9.1–9.6.1
    Printed pages 825–826 · PDF 851–852
  • PCIe Transport 1.4 · §3.1–3.4
    Printed pages 9–13 · PDF 9–13 · Figure 3–8

When you need a field guide

Existing figure explanations have canonical locations; use these links instead of duplicating the same guide.

Original documents used
  • NVM Express Base Specification · Revision 2.4 · 2026-07-31
    NVM-Express-Base-Specification-Revision-2.4-Ratified-2026.07.31.pdf
  • NVM Express NVM Command Set Specification · Revision 1.3 · 2026-07-31
    NVM-Express-NVM-Command-Set-Specification-Revision-1.3-Ratified-2026.07.31.pdf
  • NVM Express NVMe over PCIe Transport Specification · Revision 1.4 · 2026-07-31
    NVM-Express-NVMe-over-PCIe-Transport-Specification-Revision-1.4-Ratified-2026.07.31.pdf
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