NVMe Self-Study Bank: Abort, timeout and recovery
NVMe · Q1–328
Q107–Q117
Abort, timeout and recovery
A timeout is an observation, not a location. Follow submission through consumption before choosing abort or reset.
Each question is followed by its explanation. Start with the volume overview, then follow the field interpretations, comparisons or processes. Essential conditions and the normal path are visible from the start. All numerical examples are hypothetical. Status is written SCT/SC; h indicates hexadecimal.
- SCT
- Status Code Type
Find the command stage first
Missing completion proves neither nonexecution nor unchanged media.
| Stage | Evidence | Next question |
|---|---|---|
| Submitted | SQE and tail | Was it consumed? |
| Consumed | SQHD and tracking | Is it a long operation? |
| Completed | CQE and phase | Did the host miss it? |
| Recovering | Abort/reset state | Are prior effects uncertain? |
- SQE
- Submission Queue Entry
- CQE
- Completion Queue Entry
Worked interpretation: Abort targeting SQ5/CID 9 has its own Admin completion. One CQE for each is normal; duplicate target completion is different.
- CID
- Command Identifier, unique among outstanding commands in one SQ
- CQE
- Completion Queue Entry
Sources: Base 2.4 §5.2.1 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.1, 4.2.3–4.2.4
Review the terminology when needed
- Controller / namespace
- A controller receives commands and manages access. A namespace is a logical storage space that commands can address. An NVM subsystem contains controllers and nonvolatile storage resources.
- SQ / CQ / SQE / CQE
- Submission and Completion Queues carry command entries (SQEs) and completion entries (CQEs). QID identifies a queue, CID distinguishes outstanding commands in one SQ, and NSID identifies a namespace.
- Register / Identify / Feature / Log
- A register exposes control or state. Identify queries capabilities and attributes; features query or configure operation; log pages report specific state or records. FID, LID, CNS and CSI select features, logs, Identify structures and command sets.
- index / offset / zero-based
- An index selects an entry, usually starting at 0; an offset measures distance from an origin in specified units. A zero-based count encodes count−1, but not every zero-valued field is a count. A Dword is 4 bytes; a byte is 8 bits.
- Scope / reset / retention
- Scope names the affected objects; retention means preserving state. Controller Reset (clearing CC.EN) is one form of Controller Level Reset, or CLR. Different CLR triggers can retain different registers.
Questions in this volume
- Q107 · How does Abort identify its target with SQID and CID?
- Q108 · What happens when Abort targets a completed or missing command?
- Q109 · How does ACL apply to repeated and concurrent Abort commands?
- Q110 · Does successful Abort prove that the target never executed?
- Q111 · Can a target complete normally if Abort did not immediately cancel it?
- Q112 · How does the host handle racing Abort and target completions?
- Q113 · Must every timeout follow Abort, queue reset, then controller reset?
- Q114 · How should the host recover when Abort itself times out?
- Q115 · How are old commands, completions and queues handled after reset?
- Q116 · How do command, ready and long-operation timeouts differ?
- Q117 · How is a timeout located along submission, execution and completion?
Q107 How does Abort identify its target with SQID and CID?
- SQID
- Submission Queue Identifier
- CID
- Command Identifier, unique among outstanding commands in one SQ
Follow the explanation
Abort requests cancellation of a previously submitted command without necessarily resetting the controller; it does not prove the target was never executed.
1. Prepare the operation
The target can be in the Admin SQ or an I/O SQ. Abort is itself an Admin command with its own CID and completion.
- SQ
- Submission Queue
Identify.ACL is the zero-based concurrent Abort limit; queue depth does not replace it.
Abort CDW10 bits 31:16 select target CID and bits 15:0 target SQID; CDW0.CID identifies the Abort command itself.
- SQID
- Submission Queue Identifier
2. Sequence and completion conditions
Locate the target in outstanding tracking, retain its buffers, submit Abort with a distinct Admin CID and track both completions.
On successful Abort, DW0.IANP=0 reports immediate abort; IANP=1 reports no immediate abort but allows deferred abort. Inspect the target CQE too.
3. Handle unmet conditions
Excess outstanding Aborts may receive 1/03h. A missing target can be represented by successful Abort with IANP=1, not a universal Invalid Queue Identifier requirement.
If SQ3/CID 7 and SQ4/CID 7 coexist, CDW10=(7<<16)|3 targets only the former; this detects swapped fields.
Sources: Base 2.4 §5.2.1 · Base 2.4 §4.1.1 · Base 2.4 §5.2.14.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.1 · Base 2.4 §4.1.1 · Base 2.4 §5.2.14.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q108 What happens when Abort targets a completed or missing command?
Follow the explanation
A target may finish between the host deciding to abort and the controller processing Abort; absence is a normal race to handle.
1. Distinguish the failure conditions
The target is the command at the specified IDs at that time, not every historic use of those numbers.
Read Abort status and IANP and check for a target CQE. IANP=1 can mean absence or inability to abort immediately.
Do not assign a universal error status to every missing SQID/CID target; separate any independent invalid encoding in Abort itself.
2. Establish the cause from evidence
Preserve queue-lifetime and CID-allocation records so a delayed Abort is not misdirected to a later reuse.
Process an already received target completion; if it remains outstanding with IANP=1, continue tracking and retain its buffers.
3. Outcome and follow-up checks
A valid Abort can succeed with IANP=1 without cancelling the target; this reports request processing, not target success or rollback.
Replace a test requiring Abort failure for a completed target with checks of IANP and the existing target result.
First check whether the target already completed but its CQE has not been consumed.
Sources: Base 2.4 §5.2.1 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.1 · Base 2.4 §4.2.3 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q109 How does ACL apply to repeated and concurrent Abort commands?
Follow the explanation
ACL limits concurrent Abort requests, not cancellations per second or namespace count.
1. Distinguish the failure conditions
Each outstanding Abort consumes concurrent capacity, including several targeting the same command.
Track each Abort CID, target IDs and result separately. Bulk cancellation can use supported Cancel or I/O SQ deletion/recreation.
The controller may complete excess requests with 1/03h; the specification does not mandate observing that code on every over-limit test.
2. Establish the cause from evidence
ACL=0 permits one outstanding Abort and ACL=3 four; release host accounting on completion.
Check capacity before submission and wait at the limit. Repeated targets still have separate Abort CQEs but only one target completion.
3. Outcome and follow-up checks
With ACL=1, two outstanding Aborts fit the limit; submitting another after one completes avoids host overrun.
Count submissions not yet completed rather than cumulative Abort operations.
First check zero-based ACL interpretation and removal of completed requests from the count.
Sources: Base 2.4 §5.2.1 · Base 2.4 §5.2.14.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.1 · Base 2.4 §5.2.14.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q110 Does successful Abort prove that the target never executed?
Follow the explanation
No. Abort can stop further processing but is not transaction rollback; data transfer or state changes may already have occurred.
1. IANP defines the guarantee after abort
The Base 2.4 evidence is IANP in a successful Abort, not success status alone.
IANP=0 prohibits subsequent target effects after the Abort CQE, including host-memory access and media/management changes, except posting the target CQE.
Immediate abort yields target Command Abort Requested. The target CQE may precede or, under the no-subsequent-effects guarantee, follow the Abort CQE.
IANP=1 gives no no-subsequent-effects guarantee. An initiated but incomplete transfer without a posted target CQE precludes immediate abort.
2. Earlier effects still need checking
Record Abort completion and IANP, handle target completion and assess data under command semantics before retrying a possibly partially executed write.
Test prohibited effects after Abort completion rather than requiring that the target never performed any work.
Sources: Base 2.4 §5.2.1 · Base 2.4 §3.4.1–3.4.5 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.1 · Base 2.4 §3.4.1–3.4.5 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q111 Can a target complete normally if Abort did not immediately cancel it?
Follow the explanation
Yes. IANP=1 allows either deferred cancellation or normal target completion.
1. Read the Abort and target CQEs separately
Inspect IANP on successful Abort and the target CQE. Do not interpret reserved/undefined DW0 from a failed Abort as a valid IANP result.
A deferred-aborted target must report Command Abort Requested; otherwise it reports its actual execution result.
Either target success or Command Abort Requested can be valid, without a second target completion.
2. Continue tracking the target after IANP=1
After IANP=1, track the target under host recovery time limits; escalating to reset requires proper queue-lifetime and resource handling.
IANP=1 means neither that cancellation will never occur nor that it definitely will occur later.
Sources: Base 2.4 §5.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q112 How does the host handle racing Abort and target completions?
Follow the explanation
Timeout and normal completion paths can race over host tracking. Synchronize host state rather than demanding a universal completion order.
1. Prepare the operation
Abort and target have separate lifetimes; their CQEs are distinct even though they refer to one target.
Identify completions by SQID+CID, phase and queue lifetime; CID alone is insufficient across queues.
Track target and Abort completion independently; only the target result completes the target to higher software layers.
2. Sequence and completion conditions
Update the appropriate state atomically. A later Abort CQE closes Abort only; an earlier Abort CQE requires IANP and target-state handling.
Each command completes once and resources are reclaimed once. Two CQEs for two different commands are not duplicate target completion.
3. Handle unmet conditions
Do not universally require target CQE first; Base 2.4 permits either posting order when immediate-abort no-subsequent-effects conditions are met.
Verify single upper-layer completion and prevent old Abort results from affecting a reused CID lifetime.
Sources: Base 2.4 §5.2.1 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §3.3.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.1 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §3.3.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q113 Must every timeout follow Abort, queue reset, then controller reset?
Follow the explanation
There is no universal three-step sequence. Diagnose a slow command, failed queue or lost controller communication before selecting recovery scope.
1. Preserve the evidence first
Abort targets a command; queue deletion/recreation targets queues; controller reset affects all its queues and outstanding commands.
Preserve CQ position/phase, interrupts, CSTS and other-command progress. CAP.TO is not a per-I/O timeout.
- CQ
- Completion Queue
Available actions include Abort, queue deletion/recreation and reset via CC.EN, each with its own preconditions and completion checks.
2. Work through the possible causes
These branches guide the host’s recovery choice; they are not a mandatory three-step sequence.
- First inspect the CQ: is a valid completion already present?
If the host missed processing or an interrupt, consume the CQE and investigate notification.
- One command remains outstanding; Admin path works
Consider a targeted Abort, tracking its result separately from the target command.
- Queue failure with a usable management path
Recover the affected queues under Delete/Create rules, confirming old accesses have stopped before reusing memory.
- Severe Admin failure or a Delete that does not complete
Consider Controller Reset without forcing an Abort through an unusable path.
Without a CQE, a host timeout provides no DNR bit. After recovery, also check ongoing background operations; a working new queue is not the whole result.
- CQ
- Completion Queue
- DNR
- Do Not Retry, a completion retry indication
3. Connect observations to specification conditions
Recovery establishes usable new channels, resolves old-command access risks and rechecks any continuing background operations.
A host timeout is not an NVMe completion status. Do not fabricate a timeout CQE or require Abort when the Admin path cannot complete it.
Mark specification requirements separately from host-selected timeouts and escalation policies.
Sources: Base 2.4 §5.2.1 · Base 2.4 §9.1–9.6.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §5.2.1 · Base 2.4 §9.1–9.6.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q114 How should the host recover when Abort itself times out?
Follow the explanation
Now both target outcome and Admin-channel health are uncertain. Repeated Abort submissions do not establish that old commands stopped.
1. Preserve the evidence first
Recovery may widen to the controller, requiring coordination with all its queue and resource management.
Check Admin CQ phase/head, CFS/RDY and ACL accounting.
Preserve Abort CID, target IDs, timing and observed CQEs; a subsequent reset does not fabricate an Abort result.
2. Work through the possible causes
First check whether the Admin CQ is full or no longer being consumed.
Exclude missed Admin CQEs; serious Admin failure calls for controller reset, state confirmation and reinitialization under Base 9.1/9.5.
3. Connect observations to specification conditions
New commands use recovered queues; prior data effects still require command-specific persistence analysis.
Without an Abort CQE there is no IANP, DNR or More to decode. Successful reset does not prove a target write never happened.
- DNR
- Do Not Retry, a completion retry indication
Correlate registers, new queue usability and background-operation logs rather than relying only on a host reset routine’s return value.
Sources: Base 2.4 §9.1–9.6.1 · Base 2.4 §5.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §9.1–9.6.1 · Base 2.4 §5.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q115 How are old commands, completions and queues handled after reset?
Follow the explanation
Reset separates queue lifetimes; surviving memory bytes are not evidence of valid commands or completions.
1. Identify the trigger and affected objects
Rebuild affected I/O queues and outstanding tracking; stored data and independent background operations follow separate rules.
Check reset type, CC/CSTS and Admin-register retention; CC.EN-reset exceptions do not apply to every source.
2. State changes and recovery
Reset host queue pointers/expected phase and separate new submissions from old tracking; inspect continuing operations through their logs.
Stop submissions, complete reset and access-termination checks, create new queues, then resume I/O with retry analysis of possible prior effects.
New queues accept completions for their new lifetime; the host does not wait for all old CQEs after reset termination.
3. Verify retention and recovery
Reset is not universal per-command completion with one error code. Reset-aborted AERs expressly have no CQE; other commands do not universally return Command Abort Requested.
Validate new queues and termination of old-buffer accesses; new-command success alone does not exclude late old-command activity.
First inspect reused phase or tracking state that could make stale CQEs appear new.
Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §3.3.1 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.7.1–3.7.4 · Base 2.4 §3.3.1 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2) · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q116 How do command, ready and long-operation timeouts differ?
Follow the explanation
Command completion, readiness and background-operation completion are different waits; sharing one deadline causes false timeouts.
1. What differs
Host command timeouts are software policy, readiness concerns controller state and background progress belongs to the management operation.
Observe CQEs, RDY and operation logs. AER remains outstanding without an event and should not use an ordinary command timeout.
2. How to choose and verify
Disable uses CAP.TO; enable uses ready-mode and CRTO/CAP rules; interpret function estimates and maxima under their own definitions.
Name the awaited transition and timer start. After Sanitize initiation succeeds, monitor its status rather than expecting a second command CQE.
The wait succeeds when its specified state is reached; command success and media-operation completion can occur separately.
3. Conditions that shape the comparison
CAP.TO is not universal across commands, and an estimated duration is not automatically a mandatory deadline.
Record source, units, starting event and whether each timeout is an estimate or limit.
Sources: Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.1.4 (CRTO) · Base 2.4 §3.5.3–3.5.4 · Base 2.4 §5.2.1 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §5.2.14.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §3.1.4 (CAP, VS) · Base 2.4 §3.1.4 (CRTO) · Base 2.4 §3.5.3–3.5.4 · Base 2.4 §5.2.1 · Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §5.2.14.2.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Q117 How is a timeout located along submission, execution and completion?
Follow the explanation
Evidence along the command lifetime localizes missing progress before blaming slow firmware execution.
1. Preserve the evidence first
Analyze the target together with its SQ, CQ, shared vector and neighboring commands to locate shared bottlenecks.
Use SQE snapshots, tail doorbell, reported SQHD, CQ phase/head, interrupt configuration and CSTS as interface evidence.
- SQE
- Submission Queue Entry
Advanced SQHD establishes consumption, not completion of every command; a valid target CQE establishes its result, while interrupts notify the host to inspect CQs.
2. Work through the possible causes
First inspect the expected-phase CQ slot to distinguish an unreported result from an unconsumed completion.
Check visibility, doorbell update, new CQ phase and host consumption/head updates. State uncertainty when internal fetch timing is unobservable.
3. Connect observations to specification conditions
An existing CQE localizes the issue beyond execution; a doorbell write alone does not prove command fetch.
This diagnosis has no single NVMe status; preserve stage-specific evidence rather than inventing a timeout status.
Correlate valid completions, shared CQ space and interrupt masking to identify host-side stalls.
Sources: Base 2.4 §4.1.1 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §3.3.1 · PCIe Transport 1.4 §3.1–3.4 · PCIe Transport 1.4 §3.5 · Base 2.4 §9.1–9.6.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations for this question
Sources: Base 2.4 §4.1.1 · Base 2.4 §4.2.1, 4.2.3–4.2.4 · Base 2.4 §3.3.1 · PCIe Transport 1.4 §3.1–3.4 · PCIe Transport 1.4 §3.5 · Base 2.4 §9.1–9.6.1 · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Source locations and existing figure guides
Base printed page = PDF page−26; the other two use identical numbers. Locations follow the supplied PDF body and retain figure numbers. Shared pages contribute only the relevant definitions, excluding Fabrics and PCIe link/packet content.
- Base 2.4 · §3.1.4 (CAP, VS)
Printed pages 54–59 · PDF 80–85 · Figure 36–37 - Base 2.4 · §3.1.4 (CRTO)
Printed pages 72–73 · PDF 98–99 · Figure 57 - Base 2.4 · §3.3.1
Printed pages 88–91 · PDF 114–117 · Figure 73–74 - Base 2.4 · §3.4.1–3.4.5
Printed pages 101–105 · PDF 127–131 · Figure 80–81 - Base 2.4 · §3.5.3–3.5.4
Printed pages 109–113 · PDF 135–139 · Figure 84–85 - Base 2.4 · §3.7.1–3.7.4
Printed pages 120–124 · PDF 146–150 - Base 2.4 · §4.1.1
Printed pages 139–142 · PDF 165–168 · Figure 92–93 - Base 2.4 · §4.2.1, 4.2.3–4.2.4
Printed pages 144–157 · PDF 170–183 · Figure 97–105, 109 - Base 2.4 · §4.2.3
Printed pages 145–155 · PDF 171–181 · Figure 101–105 - Base 2.4 · §5.2.1
Printed pages 181–182 · PDF 207–208 · Figure 147–149 - Base 2.4 · §5.2.2
Printed pages 183–190 · PDF 209–216 · Figure 150–156 - Base 2.4 · §5.2.2 (PCIe-applicable events)
Printed pages 183–191 · PDF 209–217 · Figure 150–160 - Base 2.4 · §5.2.13.1.2
Printed pages 218–220 · PDF 244–246 · Figure 212 - Base 2.4 · §5.2.13.1.14 (header, reset, hardware, Set Feature events)
Printed pages 244–256, 258, 262–264 · PDF 270–282, 284, 288–290 · Figure 232–244, 246, 252–253 - Base 2.4 · §5.2.14.2.1
Printed pages 340–387 · PDF 366–413 · Figure 338–341 - Base 2.4 · §9.1–9.6.2.1 (PCIe-applicable rules; stop before 9.6.2.2)
Printed pages 825–828 · PDF 851–854 - Base 2.4 · §9.1–9.6.1
Printed pages 825–826 · PDF 851–852 - PCIe Transport 1.4 · §3.1–3.4
Printed pages 9–13 · PDF 9–13 · Figure 3–8 - PCIe Transport 1.4 · §3.5
Printed pages 13–16 · PDF 13–16 · Figure 9
When you need a field guide
Existing figure explanations have canonical locations; use these links instead of duplicating the same guide.
- Base 2.4 Figure 101 · Completion Queue Entry: Status Field
- Base 2.4 Figure 104 · Status Code – Command Specific Status Values
- Base 2.4 Figure 338 · Identify – Identify Controller Data Structure, I/O Command Set Independent
- Base 2.4 Figure 36 · Offset 0h: CAP – Controller Capabilities
- Base 2.4 Figure 93 · Common Command Format
- Base 2.4 Figure 97 · Common Completion Queue Entry Layout – Admin and All I/O Command Sets
Original documents used
- NVM Express Base Specification · Revision 2.4 · 2026-07-31
NVM-Express-Base-Specification-Revision-2.4-Ratified-2026.07.31.pdf - NVM Express NVM Command Set Specification · Revision 1.3 · 2026-07-31
NVM-Express-NVM-Command-Set-Specification-Revision-1.3-Ratified-2026.07.31.pdf - NVM Express NVMe over PCIe Transport Specification · Revision 1.4 · 2026-07-31
NVM-Express-NVMe-over-PCIe-Transport-Specification-Revision-1.4-Ratified-2026.07.31.pdf


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