NVMe Self-Study Bank: Power, thermal and health monitoring

NVMe · Q1–328

NVM Express Base 2.4NVM Command Set 1.3NVMe over PCIe Transport 1.4

Q188–Q204

Power, thermal and health monitoring

Power states, thermal control and health counters are related but answer different questions. Learn state and timing before warnings and workload.

Each question is followed by its explanation. Start with the volume overview, then follow the field interpretations, comparisons or processes. Essential conditions and the normal path are visible from the start. All numerical examples are hypothetical. Status is written SCT/SC; h indicates hexadecimal.

SCT
Status Code Type

Separate controls, current state and lifetime counts

A configured threshold is not a warning, and warning recovery does not clear lifetime workload.

KindExamplesComparison
ControlAPST/HCTM settingsCheck units/support
Current stateTemperature and warningCompare contemporaneous conditions
CumulativeData, busy time and power lossDifferences and quantization
APST
Autonomous Power State Transition

Worked interpretation: A 2000 ms idle threshold and 100 µs exit latency describe different phases, not a fixed per-command delay.

Sources: Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.13.1.3

Review the terminology when needed
Controller / namespace
A controller receives commands and manages access. A namespace is a logical storage space that commands can address. An NVM subsystem contains controllers and nonvolatile storage resources.
SQ / CQ / SQE / CQE
Submission and Completion Queues carry command entries (SQEs) and completion entries (CQEs). QID identifies a queue, CID distinguishes outstanding commands in one SQ, and NSID identifies a namespace.
Register / Identify / Feature / Log
A register exposes control or state. Identify queries capabilities and attributes; features query or configure operation; log pages report specific state or records. FID, LID, CNS and CSI select features, logs, Identify structures and command sets.
index / offset / zero-based
An index selects an entry, usually starting at 0; an offset measures distance from an origin in specified units. A zero-based count encodes count−1, but not every zero-valued field is a count. A Dword is 4 bytes; a byte is 8 bits.
Scope / reset / retention
Scope names the affected objects; retention means preserving state. Controller Reset (clearing CC.EN) is one form of Controller Level Reset, or CLR. Different CLR triggers can retain different registers.

Questions in this volume

  1. Q188 · What does a Power State Descriptor tell the host?
  2. Q189 · How do operational and non-operational power states differ?
  3. Q190 · How do entry and exit latency affect command waits?
  4. Q191 · How is APST configured, triggered and disabled?
  5. Q192 · How should an apparent EXLAT violation be evaluated?
  6. Q193 · How should HCTM TMT1 and TMT2 be configured?
  7. Q194 · When does thermal management start and stop?
  8. Q195 · How are power and thermal settings restored?
  9. Q196 · What do SMART Critical Warning bits mean?
  10. Q197 · How are spare capacity and percentage used interpreted?
  11. Q198 · How do SMART workload and uptime counters accumulate?
  12. Q199 · How do unexpected power-loss and error counters accumulate?
  13. Q200 · How are warning and critical temperature times counted?
  14. Q201 · How do sensor temperatures relate to Composite Temperature?
  15. Q202 · Which health changes generate asynchronous events?
  16. Q203 · How is SMART data scope determined?
  17. Q204 · How are SMART, operations, errors and PEL cross-checked?

Q188 What does a Power State Descriptor tell the host?

Follow the explanation

The host trades power against performance and wake latency. Descriptors characterize states, not the completion time of every command.

1. Establish the source and scope

NPSS enumerates controller states PS0 through PSn; a value of 4 means five states.

Establish Power Management applicability, then inspect NPSS and PSDs; ignore PSDs for a controller without support.

2. Fields, units and worked interpretation

NOPS classifies the state; MP uses its scale; ENLAT/EXLAT are microseconds. Relative performance ranks differ from scaled idle/active power and MBW/MBWS bandwidth.

Compare class and power, then transition latency, then like-for-like performance ranks.

Successful Identify supports state selection; Power Management or APST performs selection in operation.

3. Conditions that change the interpretation

A state beyond NPSS is invalid for selection. Unreported measurements are not guarantees of zero consumption or latency.

Cross-check NOPS, scales and selected state; ranks are not absolute IOPS.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q189 How do operational and non-operational power states differ?

Follow the explanation

This classifies I/O readiness, not whether the controller is completely unpowered.

1. What differs

NOPS=0 is operational; NOPS=1 is non-operational, while registers, Admin commands and permitted background work may remain active.

APST enters non-operational states; NOPPME controls background policy, not all Admin access.

2. How to choose and verify

Inspect PSD.NOPS, Power Management and Non-Operational Power State Config.

I/O causes return to the last operational state regardless of APST enablement.

I/O completes after resumption without a separate Set Features wake command per I/O.

3. Conditions that shape the comparison

Arrival during a non-operational state is not itself an invalid I/O request; selecting a nonexistent state is a configuration error.

Admin activity or temporary power above the non-operational limit requires examination of permitted operations and applicable power bounds.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q190 How do entry and exit latency affect command waits?

Follow the explanation

Separate state-transition delay from command execution time.

1. Establish the source and scope

ENLAT applies to entry and EXLAT to exit; a multi-state path cannot be reduced to its smallest value.

Read source and destination PSDs and the last operational state.

2. Fields, units and worked interpretation

Add source EXLAT and destination ENLAT in microseconds; ITPT is a separate idle delay in milliseconds.

Establish transition timing and path, then measure readiness separately from execution and host scheduling.

With hypothetical 2000 μs exit and 500 μs entry, the transition bound is 2500 μs, not a bound on the entire Read.

3. Conditions that change the interpretation

A late CQE does not define an Exit Latency Error status; isolate the bounded transition first.

CQE
Completion Queue Entry

Compare PSDs, actual source state, APST path and measurement boundaries.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q191 How is APST configured, triggered and disabled?

Follow the explanation

APST reduces power during I/O idle periods without a host command for every transition.

1. Prepare the operation

Each source state has an eight-byte entry; 32 entries occupy 256 bytes.

Check APSTA, NPSS and the target NOPS bit.

APSTE enables FID 0Ch; ITPT specifies idle milliseconds and ITPS the destination. ITPT=0 disables that source-state transition.

FID
Feature Identifier

2. Sequence and completion conditions

APST: configure the source state, then observe idle transition

Assume operational PS0 and supported non-operational PS3. Only this transition is shown.

  1. Set the PS0 entry and verify it

    Set APSTE=1, ITPT=2000 ms and ITPS=3: low Dword 0007D018h. The entry index is source PS0, not destination PS3.

  2. PS0 → no outstanding I/O and continuously idle for over 2000 ms

    These are the entry’s triggering conditions; time since the last submission alone is insufficient.

  3. Transition into PS3

    ITPT is the idle threshold before transition, not state entry or exit latency.

Get Features returns configuration, not proof that a transition occurred. ITPT=0 disables that source entry; APSTE=0 disables APST globally.

3. Handle unmet conditions

A nonzero ITPT requires a non-operational target; an operational target should cause Invalid Field in Command. APSTE=0 disables APST globally.

Get returns configuration, not transition history; background work and its power policy may prevent entry.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q192 How should an apparent EXLAT violation be evaluated?

Follow the explanation

Conformance requires matching measurement boundaries rather than attributing every host delay to the controller.

1. Preserve the evidence first

Isolate one controller, a known state path and one wake transition.

Snapshot PSDs, APST, Power Management, temperature and background activity.

Use source EXLAT and destination ENLAT; RTD3 has different power-restoration and initialization conditions.

2. Work through the possible causes

First establish whether the start timestamp marks the actual state exit.

Exclude submission delay, host scheduling, interrupt coalescing and media execution before measuring the transition.

3. Connect observations to specification conditions

Matching premises support a transition compliance finding; otherwise the evidence establishes only high end-to-end latency.

Exceeding EXLAT is not an invalid-command condition with a mandated fixed CQE.

CQE
Completion Queue Entry

Use controlled repeat measurements with timing resolution and uncertainty.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q193 How should HCTM TMT1 and TMT2 be configured?

Follow the explanation

HCTM supplies host thermal targets for lighter and heavier mitigation.

1. Prepare the operation

It controls target-controller thermal management using Composite Temperature.

Check HCTMA and the MNTMT/MXTMT supported range.

FID 10h CDW11[31:16] is TMT1 and [15:0] TMT2, both Kelvin; zero disables the respective part.

FID
Feature Identifier

2. Sequence and completion conditions

Keep nonzero values in range and TMT1<TMT2 when both are enabled; verify by Get and do not encode Celsius directly.

For a hypothetical 300–360 K range, 330/340 K is valid whereas 340/330 K reverses the thresholds.

3. Handle unmet conditions

Out-of-range enabled thresholds or invalid ordering require Invalid Field in Command.

Compare thresholds, SMART temperature and thermal counters; temperature-warning FID 04h is separate.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q194 When does thermal management start and stop?

Follow the explanation

Thresholds trigger action without prescribing one universal throttling curve.

1. Mechanism and scope

Decisions use Composite Temperature, not an arbitrary physical sensor.

At enabled TMT1 below enabled TMT2, lighter mitigation should begin; reaching enabled TMT2 shall trigger mitigation regardless of performance impact.

2. Understand it through actions and results

Check enabled thresholds, CTEMP, transition counts and accumulated seconds.

Track rising and falling temperature; vendor-specific hysteresis means crossing below TMT2 need not immediately restore full performance.

Observe consistent mitigation and thermal counters; the specific mechanism is vendor-defined.

3. Avoid a misleading conclusion

Continued throttling below TMT2 is not alone a violation; inspect TMT1, hysteresis and other protection mechanisms.

Preserve the different should/shall strengths for the two thresholds.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q195 How are power and thermal settings restored?

Follow the explanation

Distinguish saved configuration, current configuration and live thermal/power state.

1. Identify the trigger and affected objects

Treat Power Management, APST, HCTM and NOPS Config as separate features.

Use SEL=3 for capabilities and SEL=0/1/2 for Current/Default/Saved, with scope.

2. State changes and recovery

Successful SV=1 updates Saved; SV=0 changes Current only. Non-saveable features follow explicit persistence rules.

Snapshot values before reset, recover Admin access, reread settings and then validate resulting behavior.

Current matches the required restored value, not necessarily the last pre-reset SV=0 setting.

3. Verify retention and recovery

Unsupported saving follows the specified Feature Not Saveable handling; a failed Set does not establish saved state.

Restoring feature defaults does not imply clearing temperature or lifetime counters.

First inspect SV, the actual CQE and reset coverage.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q196 What do SMART Critical Warning bits mean?

Follow the explanation

Critical Warning reports current spare, thermal, reliability and read-only concerns; it is not a permanently latched history.

1. Establish the source and scope

Bits are independent and may differ from their state when an earlier AER occurred.

Read LID 02h and check the AEC SHCW enable mask and applicable hardware capabilities.

LID
Log Page Identifier

2. Fields, units and worked interpretation

Bits 0–6 indicate low spare, temperature condition, degraded reliability, all-media read-only, volatile backup failure, PMR read-only/unreliable and indeterminate personality state; bit 7 is reserved.

PMR
Persistent Memory Region

Decode asserted bits and related fields; bit 1 may indicate either over- or under-temperature.

A successful read returns the current combination; multiple warnings are valid.

3. Conditions that change the interpretation

Namespace Write Protection shall not set AMRO; an inapplicable backup bit is not failure evidence.

Correlate warning type, values and timing rather than requiring later CW to reproduce the event snapshot.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q197 How are spare capacity and percentage used interpreted?

Follow the explanation

These answer remaining spare, warning threshold and estimated life consumed, not one common percentage formula.

1. Establish the source and scope

SMART health scope is not free filesystem space in a namespace.

Read AVSP, AVSPT, PUSED and CW.ASCBT; use Endurance Group logs for group-level health.

2. Fields, units and worked interpretation

Spare and threshold range from 0–100%; the warning uses strict less-than. PUSED is a vendor estimate; 100 is not proof of failure, values may exceed 100 and values above 254 encode as 255.

Hypothetical spare 8 with threshold 10 is low spare, while PUSED=105 indicates estimated endurance consumed beyond 100%.

PUSED is updated once per power-on hour outside sleep, not after every Write.

3. Conditions that change the interpretation

PUSED above 100 is legal; equality does not satisfy a below-threshold condition.

Compare the warning with AVSP; do not derive spare directly from PUSED.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q198 How do SMART workload and uptime counters accumulate?

Follow the explanation

These counters measure different workload and uptime quantities; units precede comparison.

1. Establish the source and scope

Use SMART scope; overlapping queue activity is not added repeatedly to busy time.

Read data units, host command counts, busy time, power cycles and power-on hours with timestamps.

2. Fields, units and worked interpretation

Data units count thousands of 512-byte units rounded up; zero means not reported. Busy time counts minutes with outstanding I/O from submission doorbell to CQE posting, not host consumption.

Difference two snapshots, convert units and apply command-set classifications for completed reads/user-data-out; POH may exclude non-operational states.

A delta of two data units reflects 512000-byte quantization; a small operation need not immediately change the rounded value.

3. Conditions that change the interpretation

Application request count need not equal NVMe command count because of merging, retries and classification.

Compare actual completed commands and units rather than only file size or wall-clock time.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

Back to questions

Q199 How do unexpected power-loss and error counters accumulate?

Follow the explanation

These count power-loss conditions, unrecovered integrity errors and generated error entries separately.

1. Establish the source and scope

They are lifetime counters, not current log occupancy.

Read UPL, MDIE and NEILE alongside pre-loss SHST and any OOB media activity.

2. Fields, units and worked interpretation

Base 2.4 calls the former Unsafe Shutdowns field Unexpected Power Losses. It increments for main-power loss without SHST=10b or with media still active under the specified OOB Ignore Shutdown condition.

Establish actual main-power loss and state; separately correlate unrecovered errors with MDIE and generated entries with NEILE.

Reset without power loss does not increase UPL; completed abrupt shutdown does not alone require an increment.

3. Conditions that change the interpretation

One command failure need not increase both counters; inclusion of Write Uncorrectable-induced errors in MDIE is implementation-permitted.

Entry overwrite or recommended clearing after reset does not reduce lifetime NEILE.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q200 How are warning and critical temperature times counted?

Follow the explanation

These accumulate time in warning/critical temperature ranges, not HCTM transitions.

1. Establish the source and scope

They use operational-state composite temperature against WCTEMP/CCTEMP in minutes.

Read WCTEMP/CCTEMP and SMART WCTT/CCTT, with applicable hysteresis configuration.

2. Fields, units and worked interpretation

WCTT covers WCTEMP≤temperature<CCTEMP; CCTT covers temperature≥CCTEMP, with zero-report rules for unimplemented thresholds.

Determine the duration in each operational temperature range rather than turning one hot sample into a full minute.

For two hypothetical minutes in the critical range, inspect CCTT rather than demanding the same duration in the warning-only range.

3. Conditions that change the interpretation

WCTT is zero if WCTEMP or CCTEMP is zero; CCTT is zero if CCTEMP is zero. Zero does not universally prove no overheating.

Keep HCTM seconds separate because its thresholds, units and meaning differ.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q201 How do sensor temperatures relate to Composite Temperature?

Follow the explanation

Sensors observe different locations; Composite Temperature need not equal their maximum, minimum or average.

1. Establish the source and scope

Locations and composite computation are implementation-specific.

Read CTEMP and TSEN1–TSEN8 and the device’s sensor mapping.

2. Fields, units and worked interpretation

Values are Kelvin; a zero TSEN means unimplemented, not a valid 0 K measurement.

Remove unimplemented fields before conversion; 300 K is about 26.85°C. Pair thresholds with their selected sensors.

Different returned temperatures are valid and do not themselves imply corruption.

3. Conditions that change the interpretation

Not every TSEN must be implemented, and the composite need not be an average.

Correlate warnings, selected sensor and that sensor’s reading.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q202 Which health changes generate asynchronous events?

Follow the explanation

Health notifications reduce polling but remain subject to support, enablement and masking.

1. When the event exists and who observes it

SMART/Health events report defined warnings, not every temperature or counter change.

Inspect SHCW, CW, outstanding AERs and relevant thresholds.

Event type/information identify the condition; follow the returned LID to the associated health data.

LID
Log Page Identifier

2. Notification, reading and acknowledgment

Post requests, enable desired notices, preserve event CQEs, read/acknowledge with RAE and replenish requests.

Eligible events can complete a request; a subsequently cleared CW does not invalidate an earlier event.

3. Evaluate missing notifications or records

Missing completion requires checking enablement, masking and available requests before alleging omission.

Compare event-time settings and conditions, not only a later snapshot.

First verify the relevant SHCW bit and acknowledgment of the previous masked event.

4. Asynchronous Event notification conditions

This question concerns SMART/Health AERs: evaluate conditions, SHCW, masking and requests together. Ordinary counter increments do not require events.

Sources: Base 2.4 §5.2.2 (PCIe-applicable events) · Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q203 How is SMART data scope determined?

Follow the explanation

Scope identifies what the health values describe and prevents mistaking aggregate data for per-namespace health.

1. Select the target and information

Base 2.4 SMART/Health does not provide namespace-specific information; acceptance of different NSIDs does not create per-namespace data.

Use this revision’s SMART and Get Log rules; use the separate log for Endurance Group health.

Encode NSID/LID correctly while interpreting each field under its defined scope.

NSID
Namespace Identifier

2. Query sequence and interpretation

Record controller/NSID and compare responses; identical data across NSIDs is expected under this revision’s definition.

NSID
Namespace Identifier

Successful reads do not allocate endurance consumption to individual namespaces.

3. Handle missing or inconsistent evidence

Do not import older namespace-specific assumptions and demand distinct counters.

Compare revision, log definition and response rather than old tool labels.

First distinguish accepted NSIDs from per-namespace accounting capability.

Sources: Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2 · Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events)

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Q204 How are SMART, operations, errors and PEL cross-checked?

Follow the explanation

Cross-check meaningful relationships rather than demanding one increment in every source per operation.

1. Preserve the evidence first

Fix controller, time interval and each source’s scope before comparing.

Preserve capabilities, before/after SMART, CQEs, errors and an available PEL context.

Correlate command IDs, Error Count and PEL event data while interpreting SMART units and accumulation conditions.

2. Work through the possible causes

First verify that the operation actually triggers each expected field change.

Predict affected evidence, isolate a scenario and compare each expected relationship.

3. Connect observations to specification conditions

A normal Read may increase read/data counters without requiring an error entry or per-command PEL record.

Absence of optional evidence is not a violation; missing advertised More information requires checking overwrite, timing and logging rules.

Separate compliance, established violation and insufficient evidence.

Sources: Base 2.4 §5.2.13.1.14 (header, reset, hardware, Set Feature events) · Base 2.4 §5.2.13.1.3 · Base 2.4 §8.1.19.1–8.1.19.5 · Base 2.4 §5.2.14.2.1 (Power State Descriptor) · Base 2.4 §5.2.30.1.2, 5.2.30.1.7 · Base 2.4 §5.2.30.1.10 · Base 2.4 §5.2.30.1.6 · Base 2.4 §4.4 · Base 2.4 §5.2.30.1 (common fields, scope and persistence) · Base 2.4 §3.7.1–3.7.4 · Base 2.4 §4.2.3 · Base 2.4 §5.2.13.1.2 · Base 2.4 §5.2.2

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Source locations and existing figure guides

Base printed page = PDF page−26; the other two use identical numbers. Locations follow the supplied PDF body and retain figure numbers. Shared pages contribute only the relevant definitions, excluding Fabrics and PCIe link/packet content.

  • Base 2.4 · §3.7.1–3.7.4
    Printed pages 120–124 · PDF 146–150
  • Base 2.4 · §4.2.3
    Printed pages 145–155 · PDF 171–181 · Figure 101–105
  • Base 2.4 · §4.4
    Printed pages 166–169 · PDF 192–195 · Figure 126–127
  • Base 2.4 · §5.2.2
    Printed pages 183–190 · PDF 209–216 · Figure 150–156
  • Base 2.4 · §5.2.2 (PCIe-applicable events)
    Printed pages 183–191 · PDF 209–217 · Figure 150–160
  • Base 2.4 · §5.2.13.1.2
    Printed pages 218–220 · PDF 244–246 · Figure 212
  • Base 2.4 · §5.2.13.1.3
    Printed pages 220–225 · PDF 246–251 · Figure 213–214
  • Base 2.4 · §5.2.13.1.14 (header, reset, hardware, Set Feature events)
    Printed pages 244–256, 258, 262–264 · PDF 270–282, 284, 288–290 · Figure 232–244, 246, 252–253
  • Base 2.4 · §5.2.14.2.1 (Power State Descriptor)
    Printed pages 384–387 · PDF 410–413 · Figure 340–341
  • Base 2.4 · §5.2.30.1 (common fields, scope and persistence)
    Printed pages 456–460 · PDF 482–486 · Figure 463–466
  • Base 2.4 · §5.2.30.1.2, 5.2.30.1.7
    Printed pages 460–462, 468–469 · PDF 486–488, 494–495 · Figure 468–469, 475–478
  • Base 2.4 · §5.2.30.1.6
    Printed pages 466–468 · PDF 492–494 · Figure 474
  • Base 2.4 · §5.2.30.1.10
    Printed pages 471–472 · PDF 497–498 · Figure 482
  • Base 2.4 · §8.1.19.1–8.1.19.5
    Printed pages 666–671 · PDF 692–697 · Figure 738–741

When you need a field guide

Existing figure explanations have canonical locations; use these links instead of duplicating the same guide.

Original documents used
  • NVM Express Base Specification · Revision 2.4 · 2026-07-31
    NVM-Express-Base-Specification-Revision-2.4-Ratified-2026.07.31.pdf
  • NVM Express NVM Command Set Specification · Revision 1.3 · 2026-07-31
    NVM-Express-NVM-Command-Set-Specification-Revision-1.3-Ratified-2026.07.31.pdf
  • NVM Express NVMe over PCIe Transport Specification · Revision 1.4 · 2026-07-31
    NVM-Express-NVMe-over-PCIe-Transport-Specification-Revision-1.4-Ratified-2026.07.31.pdf
Jia-Chang

Jia-Chang

Human

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