PCIe Chapter 11: Hot-Plug and Topology Changes

Connect insertion to a usable function

Managed hot-plug connects presence, power, link readiness and software configuration. Chapter 3/4 enumeration and resource allocation are reused after the applicable link and reset waits.

Specification route: Slot implementation and hot-plug capability → Figures 7-30–7-32 → Section 6.7.3 operations and notification → enumeration and resources.

Start capability discovery at the Port that manages the slot

After locating the PCI Express Capability at 0x70 on 02:01.0, use Figure 7-23 for Port Type and Slot Implemented, then Figure 7-30 for Slot Capabilities. Do not search the Endpoint for its parent slot controller. Physical elements depend on the form factor; Base does not require identical buttons, latches, and indicators everywhere.

0x0162 means Version=2, Type=6, and Slot Implemented=1. Slot Capabilities bits 0–4 indicate an Attention Button, Power Controller, MRL sensor, and both indicators. MRL means Manually-operated Retention Latch. Bit 6 declares Hot-Plug capability; bit 18=0 indicates Command Completed support. Bits 31:19 identify physical slot 5, not Device Number. Power Limit Value=75 and Scale=0 specify a 75 W limit, not measured consumption.

HPS bit 5=0, so this example demonstrates orderly operation. This bit alone does not classify every asynchronous-removal architecture: Base 6.0 deprecates the old HPS mechanism for async hot-plug and recommends DPC. SFI can also suppress the HPS read value.

DPC

Downstream Port Containment

Separate current state, pending events, and notification

Slot Status=0x0048 has Presence Detect State bit 6 and Presence Detect Changed bit 3 set. One reports current presence; the other records a pending event. Further slot events of the same type are ignored until that pending event is cleared. A bit is therefore neither a counter nor a complete history.

Out-of-band detection detects insertion while main power is off in this example. Generally, with In-Band PD Disable=0, Presence is the OR of in-band and applicable out-of-band detection; in-band detection requires power. Presence=1 does not establish Link Active.

0x17F8 enables Presence Changed, Command Completed, DLL State Changed, and the Hot-Plug master interrupt enable. Recording an event is distinct from receiving an interrupt, which additionally depends on the selected INTx or MSI/MSI-X enable, vector, and routing conditions.

MSI

Message Signaled Interrupt

MSI-X

Message Signaled Interrupts Extension

Preserve and process the evidence before writing 1 to selected RW1C bits. Presence is read-only. Recheck concurrent changes; do not indiscriminately perform a 32-bit read-modify-write across adjacent Control and Status.

Command completion does not authorize immediate enumeration

With the latch closed, sufficient power budget, and no previous command pending, the example writes Slot Control=0x12F8: Power On, Power Indicator Blink, Attention Indicator Off, with notification settings preserved. Any Slot Control write is a hot-plug command. Since Command Completed is supported, wait for the preceding command before another write. After one second without completion, the specification permits retrying or issuing the next command; this does not prove power succeeded.

Power Controller Control readback is not a power measurement; faults can prevent power-up. After DLL State Changed, read Link Active before configuration access. The one-second DLL-change deadline starts at the Power On write here. Declaring an already-active device broken for not returning Successful Configuration Completions requires allowing at least one second from Active. These deadlines answer different questions.

Configuration access still requires usable resources afterward

Suppose only 0x80080000–0x800FFFFF remains available along the path: 0x80000 bytes, or 512 KiB. A new size-aligned BAR requiring 0x100000 bytes, or 1 MiB, cannot fit even if Configuration Requests succeed. Writing a BAR outside a Bridge Window does not automatically extend forwarding.

BAR

Base Address Register

Reserving Bus Numbers and address ranges can help. Reallocation depends on Host Bridge resources, every intervening window, and software coordination. This is an author-created system deduction, not a guarantee that every hot-added card fits. Chapters 3–4 cover enumeration and BAR calculation.

When is it safe to remove the card after pressing the button?

The Attention Button requests a hot-plug operation. When software accepts removal, it blinks the Power Indicator to acknowledge the request and allow cancellation. Software then coordinates device quiescence, powers the slot down and observes the required wait before allowing physical removal.

Clear the first button event so a second press can be recorded

Figure 7-32 and Table 7-29 place Attention Button Pressed in Slot Status bit 0, with RW1C behavior: writing 1 clears the bit. Assume Slot Status reads 0x0041: presence and the button event are set, with all other bits zero. The example saves the event, then performs a 16-bit write of 0x0001 to 0x8A to clear only that event. Under §6.7.3.1, further events of the same type are ignored while one remains pending. Leaving the first press pending prevents a second press from producing a new event record.

Next, §6.7.1.5 starts the five-second abort interval when the Power Indicator begins blinking after software accepts the request. A second press during that interval cancels the operation. The cancellation branch in this example keeps device power on and restores the steady-on indicator under the command completion rules. The interval begins at the start of blinking, rather than at interrupt delivery or a later Status read.

After the cancellation interval, quiesce device work

This example starts quiescence after five seconds without cancellation: stop accepting new work and coordinate outstanding reads, writes, direct memory access (DMA) and interrupts with the driver and device. That scheduling is an author-created system flow. Queue shutdown, cancellation and data preservation depend on device and software documentation. If quiescence has not succeeded, remain at this step and keep removal prohibited.

DMA

Direct Memory Access, device access to memory

For example, clearing Bus Master Enable constrains subsequent relevant Requests from the Function. Earlier Memory Reads, Posted Writes already in the path, and application data still need their respective completion or preservation evidence. Slot Status alone does not provide those device and software guarantees.

Command completion does not end the power-off wait

Figure 7-31 and Table 7-28 define Power Controller Control=1 as the Power Off request. Power Indicator Control=10b keeps the indicator blinking. Both fields can be written in one Slot Control command, but the order of its actions is unspecified. The indicator is already blinking before this example requests power off.

This slot supports Command Completed, so §6.7.3.2 requires waiting for the preceding command to complete before issuing the next Slot Control command. Section 6.7.1.8 separately requires at least one second after turning power off before any action that relies on power removal. Software must not turn the Power Indicator off or attempt to turn power back on before that wait completes.Command Completed makes the controller ready for another command; the power-off wait still applies. Control readback reports the last written request, not a voltage measurement.

Once the power-off wait and applicable removal conditions are satisfied, software sets Power Indicator Control=11b to turn the indicator off. Table 6-9, Power Indicator States, gives the user-facing meaning: blinking means an operation is in progress and insertion or removal is prohibited; Off permits insertion or removal. Which supplies and signals must be removed depends on the slot's form-factor specification. Auxiliary power or other signals may remain present.

The table describes known outcomes at successive stages of this scenario. A snapshot containing only Command Completed=1, Power Controller Control=1 and Presence Detect State=1 shows command-interface readiness, the last power-off request and detected card presence. The control-write and processing timeline is still needed to establish whether the power-off wait completed.

If the device disappears asynchronously, access may be lost before this coordination completes. Software must handle invalidated state and outstanding work. DPC can contain downstream error propagation; device and software evidence still determines application and data-preservation outcomes. See Chapter 12 for containment and recovery, rather than repeating the orderly button sequence.

DPC

Downstream Port Containment

Check the interpretation