PCIe Chapter 9: Reset Scope and Recovery Conditions

Follow the normal reset sequence

Chapters 6–8 established memory access, interrupt notification, and Link operation. Here, keep that Link running while rebuilding the target Function. The reading route follows the software task: Figure 7-24 for support, Figure 7-26 for outstanding traffic, Figure 7-25 for the trigger, then §6.6.2 for waiting and restoration.

1. Check Function Level Reset (FLR, the per-Function mechanism) support in Device Capabilities bit 28.
2. Coordinate other accessors, stop new work, and handle existing Requests. The example in the implementation note on p.727 clears Command and checks Transactions Pending, which tracks outstanding Non-Posted Requests requiring Completions.
3. Write Initiate FLR in Device Control. The Function completes this Configuration Write before starting reset.
4. In this example, wait 100 ms, then attempt Configuration access. If subsequent initialization still needs time, Request Retry Status (RRS) tells software to retry later. Satisfy any remaining old-transaction wait before initialization.
5. Restore fields by their access rules, rebuild the device interface and notification path, then resume work.

The following sections explain the field values and exceptions along this route.

Preserving another Function requires the right reset scope

If 03:00.1 must keep working, first discover FLR support in 03:00.0. Secondary Bus Reset on 02:01.0 affects both; operating above the Switch can broaden scope. PERST# board timing needs the relevant platform/form-factor specification. Physical Function (PF) FLR clears Virtual Function (VF) Enable, making the associated VFs cease to exist; ordinary-Function isolation must not be generalized to that relationship.

Discover support, handle pending traffic, then trigger FLR

Read Figure 7-24/Table 7-20, Figure 7-26/Table 7-22, then Figure 7-25/Table 7-21. After quiescing and required waits, a 16-bit write of 0x2810 | 0x8000 = 0xA810 triggers FLR without writing adjacent read/write-one-to-clear (RW1C) Status. Initiate FLR always reads zero. That bit means something else in a PCIe-to-PCI/PCI-X Bridge, so Function type is a prerequisite.

Stopping new Requests does not remove old Completions

Bus Master Enable (BME)=0 does not recall Requests already sent. Transactions Pending tracks this Function's Non-Posted Requests, which may complete or terminate through timeout. It does not cover all Posted Writes, CPU accesses, or external work, and FLR completion itself must clear it.

In the authored scenario, FLR occurs before an old Memory Read (MRd) with transaction Tag=0x13 returns. Immediate Tag reuse could misassociate a late Completion with a new transaction. Software must coordinate other accessors, stop device work and Direct Memory Access (DMA) and interrupt activity, then handle outstanding transactions. The p.727 Implementation Note offers an algorithm that clears Command and polls Pending or waits sufficiently before FLR; it does not replace device-specific quiescence.

FLR completion, readiness, and old-transaction waits are separate

The initiating Configuration Write must receive its Completion before FLR starts. The Function must complete FLR within 100 ms, but subsequent device-specific initialization can take longer. If it still needs initialization after that limit, it must return Request Retry Status (RRS) for Configuration Requests. After returning a non-RRS Completion, it cannot return RRS again until another reset.

If Transactions Pending=1 at initiation, software must allow old Completions to arrive or reach reasonable certainty that they will not arrive before initialization. Using the pre-FLR Completion Timeout is recommended. If timeout was disabled, the delay is system dependent but at least 100 ms. Function Readiness Status (FRS) Configuration-Ready can permit earlier Configuration access without proving all prior Requests completed. Requests during FLR may be silently discarded; arbitrary memory-mapped I/O (MMIO) polling is not a standard completion indication.

MMIO

Memory-Mapped I/O, mapped device-register access

Conventional Reset uses different timing origins. Without Device Readiness Status (DRS) or another applicable early-readiness exception, a Downstream Port supporting above 5 GT/s requires at least 100 ms after Link training completes. Authored example: reset ends at t=0 ms, training finishes at t=40 ms, and the first Configuration Request is no earlier than t=140 ms. The corresponding branch for a Port supporting only up to 5 GT/s counts from reset exit. Without Readiness Notifications, at least 1 s after Conventional Reset exit must be allowed before declaring failure from missing Successful Completion; this is distinct from first-access timing.

Interpret retained fields before restoring operation

Read the FLR rules and exceptions in §6.6.2, then interpret field attributes using Table 7-2. Some request-enabling controls are cleared, while particular settings and error records are preserved. Check each field before deciding what software needs to restore.

Use before-and-after snapshots to explain a retained error

Follow bit 14 in Figure 7-155 into Table 7-135, then read the RW1CS definition in Table 7-2. Default=0 does not remove the preservation rule. Under the example assumptions, the post-FLR 1 is the retained old record. Incomplete event or write history would require checking whether a new error occurred.

After saving the error evidence, a 32-bit write of 0x00004000 to 0x104 clears only bit 14. Other defined status bits receive zero and are unaffected by that clear operation. With no new error, bit 14 subsequently reads zero; the saved evidence still records the Timeout. See Chapter 12 for snapshots and related AER fields.

AER

Advanced Error Reporting

§6.6.2 contains the complete preservation list, including Max_Payload_Size, Active State Power Management (ASPM) Control, Read Completion Boundary (RCB), hardware-initialized (HwInit), and sticky fields; Flit-capable implementations have additional requirements. Physical and Data Link state machines and Virtual Channel 0 (VC0) remain intact. Cold/Warm Reset and auxiliary-power preservation conditions need their own checks.

Handle read-only (RO), write-one-to-clear (RW1C), sticky write-one-to-clear (RW1CS), trigger controls, and writable settings according to their rules. Rebuild device interfaces, interrupts, and DMA conditions before restarting work. FLR does not clear host buffers for software or define every device's queue reconstruction.

DMA

Direct Memory Access, device access to memory

Check the scope