PCIe Chapter 7: From Device Events to Interrupt Service

Interrupt mechanisms and their configuration

INTx (legacy level-interrupt emulation) uses Assert_INTx/Deassert_INTx Messages. MSI (Message Signaled Interrupts, notification by memory write) and MSI-X write a system-specified DWORD (four bytes) to a system-specified address, using a Memory Write (MWr) transaction, without an ordinary Completion response. Msg/MsgD are Message packet types without/with data used by the INTx level-emulation mechanism. Interrupt-generating Functions must support MSI, MSI-X, or both; INTx is optional compatibility support. MSI and MSI-X must not be enabled simultaneously, and neither permits INTx service requests while enabled.

A separate MSI memory-write notification example has ID=0x05 and Message Control=0x0184: Multiple Message Capable (MMC)=010b requests four vectors, Multiple Message Enable (MME)=000b, and MSI is disabled. It supports 64-bit Address and Per-Vector Masking (PVM, individual vector masks) but not Extended Message Data. System software may allocate two vectors with MME (allocated vector count)=001b while MSI is disabled, complete configuration, and enable it. MSI supports up to 32 vectors with power-of-two encoding; MSI-X Table Size uses N−1.

Find the Memory Space table through the Capability

The low three BAR Indicator Register (BIR, BAR selection) bits select the BAR. BIR selects the register that supplies the table base. Masking them leaves the byte offset, without another left shift. Table base=0x80006000; its 8 × 16 bytes occupy 0x80006000–0x8000607F. The Pending Bit Array (PBA, one waiting-message bit per entry) base=0x80007000; its one required QWORD (eight bytes) occupies 0x80007000–0x80007007. Both fit within BAR0 without overlap. The example places ordinary Registers and MSI-X structures in separate naturally aligned 4 KiB regions.

Entry 3 is the fourth entry, starting at 0x80006000 + 3 × 16 = 0x80006030. Offsets +0x00, +0x04, +0x08, and +0x0C hold Message Address, Upper Address, Data, and Vector Control. Example values are 0xFEE01000, 0x00000000, 0x00000045, and initially 0x00000001. Preserve other Vector Control bits and clear Mask only at the appropriate point.

The entry address differs from the interrupt destination. The device ultimately writes 0x00000045 to platform-assigned 0xFEE01000 with all four bytes enabled, without modifying low Data bits. The value 0x45 is not a Table index; this example defines no CPU number or interrupt-controller encoding for it. Relaxed Ordering (RO) and No Snoop, which affect ordering and cache snooping, must be clear.

Control notification before unmasking the entry

The authored initialization starts with inactive event sources. System software sets Function Mask, reading Control=0x4007; fills valid Address/Data with entry Mask=1; enables MSI-X while keeping Function Mask set, reading 0xC007; ensures configuration visibility under platform I/O rules; then clears entry 3 Mask and Function Mask, finally reading 0x8007. Other entries remain masked, and work starts only after the notification path is ready.

This is not the only valid sequence. System software manages MSI/MSI-X Message Control read/write (RW) fields; the specification prohibits device drivers from directly modifying them. Table/PBA accesses must use aligned full DWORDs (four bytes) or QWORDs (eight bytes). Address, Data, and applicable Steering Tags must not change in an unmasked entry. To mask a currently unmasked entry, first update Vector Control with a DWORD write, without simultaneously changing Data and Mask using a QWORD.

Pending records a waiting message, not an event count

With MSI-X enabled and entry 3 effectively masked, an event that would require notification must set PBA bit 3 without sending that message. If all other bits are clear, the QWORD reads 0x0000000000000008; repeated events may leave the same value. Unmasking while the event remains pending requires scheduling the message and clearing Pending after transmission. If the underlying event is satisfied while still masked, Pending must clear to avoid an unnecessary notification.

Software should only read Pending bits; writes have undefined results and are not read/write-one-to-clear (RW1C). PBA=0 also does not mean CPU service is complete. Repeated messages for one vector are not guaranteed individual service; event counting and handshakes belong to the device interface.

The example's data writes and MSI-X share one Function and TC0 (Traffic Class 0), so the interrupt write cannot pass earlier Posted writes. The system must let its interrupt handler observe updates arriving before the message, without a device-register read to flush those writes. Chapter 6's mapping and synchronization conditions still apply. Different TCs require additional synchronization. Message arrival order guarantees neither service order nor fixed latency.

What if two entries share a vector and only one is masked?

An MSI-X Mask bit belongs to a Table entry. If two entries use the same Message Address/Data pair, they share a vector; masking one entry does not automatically mask the other.

Read Table 7-55 for an entry’s Mask bit, then §6.1.4.5: when several entries share a vector, all of those entries must be masked to guarantee that the Function will not send using that Address/Data pair. Use Figure 7-67/Table 7-56 to locate each entry’s Pending bit and follow the rules for events satisfied or newly raised while masked. Function Mask=1 makes all entries behave as masked without rewriting their individual Mask bits. (Base 6.0, printed/PDF pp.664–665 and 1026–1027.)

Follow the notification path