發送端符合規格，為什麼接收端還要另做測試？
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PCIe Chapter 21: Receiver, Channel, and Reference Clock
Rx (Receiver) operates on the signal after the channel. Receiver capability must be evaluated with channel loss, equalization, and Refclk (Reference Clock) conditions. A transmitter waveform alone does not characterize the complete signal path.
Author-drawn relationships: real receiver path above, separate calibration-model path below. Models are not appended to the measured DUT output.
Separate the calibrated eye from the receiver result
Rx (Receiver) testing first establishes a prescribed stressed input, then tests the actual receiver. A stressed eye combines specified channel loss, jitter, and interference. Successful calibration prepares the stimulus; it does not supply the DUT (Device Under Test) result.
Section 8.4.1 defines the recovered eye at the receiver latch input. At 2.5/5.0 GT/s this corresponds to Rx pins. At 8.0/16.0/32.0/64.0 GT/s it corresponds to the Rx die-pad signal after behavioral equalization. Measurement plus models constructs this inaccessible reference point.
The worked case uses 16.0 GT/s and builds on the preceding chapter's voltage/reference-plane explanation.
Base 6.0 §8.4.1 Receiver Stressed Eye Specification (p.1357); §8.4.2.1 Procedure for Calibrating a Stressed EH/EW Eye (pp.1376–1379); §8.4.2.2 Procedure for Testing Rx DUT (p.1382 onward).
16.0 GT/s Endpoint: from the channel row to DUT testing
Simulated data: Author-created teaching data, not device or platform measurements. The DUT is an Endpoint supporting 32.0 GT/s. Test one Rx Lane at 16.0 GT/s with Common Refclk (CC). A test source drives the Endpoint; channel and eye values below are assumed.
1. Select the row by the receiving component
In §8.4.1.2 select 16.0 GT/s Non-Root Port in Table 8-8, because the DUT is an Endpoint. The source's location does not choose the row. Nominal channel loss is 4.2–5.2 dB at 1 GHz and 24.5–25.5 dB at 8 GHz. The Root Port high-frequency row differs.
| Frequency | Assumed SDD21 | Positive loss magnitude | Selected nominal range |
|---|---|---|---|
| 1 GHz | −4.7 dB | 4.7 dB | 4.2–5.2 dB |
| 8 GHz | −25.0 dB | 25.0 dB | 24.5–25.5 dB |
SDD21 describes differential-input to differential-output transmission. Negative dB here records attenuation, while the table lists positive loss. These two samples fit their nominal ranges but do not verify the complete mask, return loss, or other channel conditions. Figure 8-27 illustrates 8.0 GT/s; use its axes and boundaries as a reading example, and Table 8-8 for the actual 16.0 GT/s values.
The channel must also provide a series of loss options covering at least 2 dB below the high-frequency nominal minimum through 3 dB above the maximum. This case therefore needs at least 22.5–28.5 dB, with adjacent options no more than 0.5 dB apart. Those options support stress adjustment; a lone 25 dB result does not finish eye calibration.
2. Follow TP2 and TP2P separately in Figure 8-26
The upper calibration path runs from the source through the calibration and Replica Channels to TP2. Post-processing adds behavioral Rx package, equalization, and CDR (Clock and Data Recovery) models to construct the TP2P recovered eye. These models do not mandate matching internal DUT circuitry.
The lower path is used after calibration: reconnect the source to the actual DUT's Breakout Channel, then obtain its BER (Bit Error Rate). The upper-path package/equalization models are not physical components after the DUT and are not applied again to its measured BER.
Record each loss reference separately. Section 8.4.1.2 describes calibration-channel SDD21 from TP3 to TP2. Section 8.4.2.1 specifically retains TP1–TP3 cable loss in the 16.0 GT/s total-channel methodology, while 32.0/64.0 GT/s treat that cable as part of the generator. The two nominal channel samples above do not replace the total loss used at every later step.
3. Read Table 8-10 with Notes 4 and 8
In the 16.0 GT/s column, TRX-UI=62.5 ps, target eye width TRX-ST=0.30 UI, and target eye height VRX-ST=15 mVPP. EH means Eye Height and EW means Eye Width, giving nominal width 0.30 × 62.5 = 18.75 ps.
Note 4 references these targets to TP2P. Raw TP2 opening is not the target quantity. Note 8 turns common-mode interference off for EH/EW calibration and on for the stressed-eye jitter test. Here VRX-CM-INT is a 120 MHz, 150 mVPP single tone, measured at TP2 without post-processing.
Next follow the 16.0 GT/s procedure in §8.4.2.1: establish the applicable stresses and initial channel, select a Tx preset (predefined equalization setting) using modeled eye area, increase channel loss, then reselect the preset and adjust Sj (Sinusoidal Jitter), differential interference, and swing to a legal final combination. Figure 8-42 places these controls at the source, channel, and processing blocks.
4. Repeated measurements check a calibration window
Assume the other calibration steps and tool requirements have been completed for these conditions. The following excerpt gives five TP2P results for one final setting, evaluated by post-processing at the 10−12 BER condition. Actual DUT errors are measured in step 5. The procedure requires at least five measurements, with enough measurements for stability. Final 16.0 GT/s mean EH must be 15 ± 1.5 mV and mean EW 18.75 ± 0.5 ps.
| Calibration quantity | Five assumed values | Mean | Final mean window |
|---|---|---|---|
| EH | 14.5, 15.0, 15.5, 15.2, 14.8 mVPP | 15 mVPP | 13.5–16.5 mVPP |
| EW | 18.5, 18.8, 18.9, 18.6, 18.95 ps | 18.75 ps | 18.25–19.25 ps |
Both means fit their final windows. With channel, stress, and preset-selection steps also complete, this setting can be used for DUT testing. An out-of-window result first returns to stimulus adjustment; the Endpoint receive result has not yet been obtained at that stage.
- EQ
- Equalization
5. Reconnect the DUT and check the test coverage
Section 8.4.2.2.1 requires the BERT (Bit Error Rate Tester) Tx to send Modified Compliance Pattern. The calibration preset is fixed during calibration, while DUT testing permits the specified optimization with the real receiver. Common-mode and other stresses must also use their test-stage settings. Section 8.4.2 requires other DUT PCIe Lanes to send or receive data; activity on other supported I/O is recommended.
This case uses 16.0 GT/s CC and a device supporting 32.0 GT/s, so read Figure 8-45 for the Sj mask. Follow its frequency and Sj-amplitude (UI) axes, then the surrounding rules: after initial CDR lock, apply the specified swept-Sj conditions. Test 33 kHz separately rather than leaving that tone on during other frequency measurements. For 16.0 GT/s, the additional 210 MHz tone uses the calibration's 100 MHz Sj amplitude minus 0.1 UI; omit that tone if calibration Sj was below 0.1 UI. Carry this value forward from the calibration record, not just its final EH/EW.
Assume the DUT report preserves only “CDR locked” and “no observed errors at one swept-frequency point.” Test volume, error counts, other selected points, and complete stress conditions are still missing. At 16.0 GT/s the target is BER 10−12 over the applicable range. The specification does not require testing every continuous frequency, but recommends enough points to catch possible resonances and explicitly requires 33 kHz. One zero-error summary is insufficient.
Base 6.0 §§8.4.1.1–8.4.1.2, Figure 8-26 Rx Test board Topology for 16.0 and 32.0 GT/s, Table 8-8 Calibration Channel IL Limits (pp.1357–1361); §8.4.2.1, Figure 8-42 Layout for Calibrating the Stressed Jitter Eye at 16.0, 32.0, and 64.0 GT/s (pp.1376–1379); Table 8-10 Stressed Jitter Eye Parameters, Notes 4/8 (p.1380); §8.4.2.2.1 Sj Mask (pp.1382–1385), Figure 8-45 (p.1385).
Connect calibration channels to the platform-channel boundary
The preceding calibration channel generates a receiver-test stimulus. Platform-channel compliance follows §8.5.1. A captive channel is one whose full Tx-pin to Rx-pin path is comprehended by the platform design. Split-board/component designs refer to the appropriate form-factor specification, such as CEM, which takes precedence for that allocation. No unprovided form-factor values are imported here.
Follow Figures 8-56/8-57 from channel characteristics through behavioral Tx/Rx package models to a die-pad-to-die-pad topology. Include the victim path and enough aggressor paths to capture crosstalk, then apply the appropriate Tx conditions, equalization, and clock recovery.
Figure 8-57's official title names only 8.0 and 16.0 GT/s; neighboring text supplies 32.0/64.0 GT/s requirements. The 16.0 GT/s channel model uses a first-order CTLE (Continuous-Time Linear Equalizer) and two-tap DFE (Decision Feedback Equalizer) as a minimum-capability model. This is not mandated DUT circuitry, nor the preceding chapter's Tx test channel.
Base 6.0 §8.5.1 Channel Compliance Testing (pp.1400–1402); Figures 8-56 Flow Diagram for Channel Tolerancing at 2.5 and 5.0 GT/s and 8-57 Flow Diagram for Channel Tolerancing at 8.0 and 16.0 GT/s (p.1401); §8.5.1.1 Behavioral Transmitter and Receiver Package Models (p.1402 onward).
Keep clock architecture in the analysis
Refclk (Reference Clock) is more than a connection on a drawing. Common Refclk in §8.6.6 distributes one source to Tx and Rx, so some low-frequency movement propagates jointly. Relative timing at the latch also depends on Tx/Rx PLLs (Phase-Locked Loops), CDR, and transport-delay differences.
In Figure 8-89 locate the common source branches and the difference between transmitted data and receiver sampling-clock paths. Section 8.6.5 separates edge filtering, which reduces measurement-sampling artifacts, from behavioral filtering by PLLs, CDR, and applicable transport delay. Their combination yields effective Refclk jitter at the latch rather than a simple sum of raw jitter.
Section 8.6.4 does not define matching Refclk transfer functions and jitter limits for Independent Refclk (IR) there; other transmitter and receiver requirements still apply. Changing this case to IR requires a new Sj profile/model selection rather than reusing CC Figure 8-45. See Chapter 20 for the already explained Tx clock-sampling table.
Refclk testing in §8.6.1 tests the clock source, while the worked case tests the Rx. Keep each test's reference point and result separate before connecting them into one analysis.
Base 6.0 §8.6.1 Refclk Test Setup (p.1420); §§8.6.4 Refclk Architectures Supported and 8.6.5 Filtering Functions Applied to Raw Data (p.1426); §8.6.6 Common Refclk Rx Architecture (CC), Figure 8-89 Common Refclk Rx Architecture for all Data Rates Except 32.0 and 64.0 GT/s (p.1428).
Edition and sources
PCI Express Base Specification Revision 6.0 (6.0-1.0-PUB) is the authority. Printed and PDF-viewer pages match at these locations. Assumed readings and stage excerpts are author-created, not measurements or certification.
Reading locations and purpose
- §8.4.1 (p.1357): recovered-eye reference points; §§8.4.1.1–8.4.1.2, Figure 8-26, Figure 8-27 Example Calibration Channel IL Mask Excluding Rx Package for 8.0 GT/s, Table 8-8 (pp.1357–1361): channel and reference points.
- §8.4.2 Stressed Eye Test, §8.4.2.1 (pp.1376–1379): source/channel/preset/stress adjustments; final 16.0 GT/s mean windows on p.1377 and cable inclusion on p.1376.
- Table 8-10 (pp.1380–1381): targets, units, Notes 4/8; §8.4.2.1.1 Post Processing Tool Requirements (p.1381): tool consistency.
- §§8.4.2.2 / 8.4.2.2.1 (pp.1382–1385): DUT pattern, lock, and Sj test; Figure 8-45 Sj Mask for Receivers Operating in CC mode at 16.0 GT/s (p.1385).
- §8.5.1, Figures 8-56/8-57 (pp.1400–1402): platform boundary and minimum models; §8.6.1, §§8.6.4–8.6.6, Figure 8-89 (pp.1420, 1426–1428): Refclk setup, architecture, and filtering.
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