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PCIe Chapter 20: Transmitter Electrical Requirements
Tx (Transmitter) limits depend on the measurement reference point, clock architecture, rate, and test pattern. Begin with the path in Figure 8-1, then connect voltage, equalization, and jitter to the applicable conditions.
Connect the accessible point to the specified reference plane
In Figure 8-1 locate the DUT (Device Under Test) Tx pins, the Breakout Channel leading to connectors, and accessible point TP1. A waveform captured at TP1 includes that channel's effects.
Next locate the Replica Channel and its TP2/TP3 ends. It reproduces the breakout path's electrical characteristics to help refer measurements to the pins; it is not another series path traversed by Tx data. Section 8.3.1.1 de-embeds voltage parameters to pins unless stated otherwise.
De-embedding removes measurement-path effects using channel characteristics. It is not subtraction of a fixed voltage or jitter value. Section 8.3.5.2 also explains high-frequency noise amplification and the applicable processing limits.
Record the DUT/Lane, rate, full/reduced swing, pattern, clock architecture, measurement point, and processing before comparing a report with a parameter limit.
Base 6.0 §8.3.1 Measurement Setup for Characterizing Transmitters, Figure 8-1 Tx Test Board for Non-Embedded Refclk (p.1318); §8.3.1.1 Breakout and Replica Channels (pp.1319–1320); §§8.3.5.1–8.3.5.2 (pp.1336–1337).
Choose sampling and processing from the clock architecture
Refclk (Reference Clock) location, availability at DUT pins, and SRIS testing (separate reference clocks with independent spread spectrum) affect the method. In Table 8-5 select the column and row before reading their intersection.
| Selected conditions | Table 8-5 position | Sampling and processing |
|---|---|---|
| Non-Embedded Refclk; available at DUT pins; not testing SRIS | Right column, first row | 1-port measurement, CC CDR, clean external Refclk |
| Embedded Refclk; available at DUT pins; not testing SRIS | Left column, first row | 2-port measurement, CC CDR, PLL (note 1), and 10 ns transport delay |
CDR (Clock and Data Recovery) here is the processing model; CC means Common Clock. The second row captures Tx data and Tx Refclk simultaneously to remove shared clock jitter. This choice is separate from D+ and D− being two conductors. Obtain PLL (Phase-Locked Loop) characteristics from the rate-specific Refclk section and transport delay from §8.6.6; do not silently set the latter to zero.
For Independent Refclk (IR), §8.3.5.3 requires single-port jitter measurement with the appropriate model CDR. The table above reads only two selected combinations; use the full table for others. A DUT supporting several Refclk modes needs testing in each supported mode.
Base 6.0 Figure 8-2 Tx Test board for Embedded Refclk (p.1319); §§8.3.5.3 Independent Refclk Measurement and Post Processing and 8.3.5.4 Embedded and Non-Embedded Refclk Measurement and Post Processing, Table 8-5 Tx Measurement and Post Processing For Different Refclks (p.1338).
Identify the voltage quantity before looking up its limit
Read §8.3.2, then Figure 8-3. D+ and D− are individual single-ended voltages. Subtract them for differential voltage and average them for common mode.
VDIFF = VD+ − VD−; VCM = (VD+ + VD−) / 2. Peak-to-peak voltage, written mVPP here, is the maximum minus minimum of the same quantity. Equation 8-1's VDIFFp-p = 2 × max|VD+ − VD−| specifically assumes a symmetric differential swing.
Figure 8-3 relates these waveforms; it does not let an arbitrary curve height stand in for a specified Tx measurement. Follow the applicable §8.3.3.6 or §8.3.3.7 method, then select the rate, parameter, and units in Table 8-6.
Base 6.0 §8.3.2 Voltage Level Definitions, Equations 8-1 VDIFFp-p and 8-2 VTX-AC-CM-PP (p.1320); Figure 8-3 Single-ended and Differential Levels (p.1321).
Why does 450 mVPP single-ended become 900 mVPP differential?
Simulated data: Author-created teaching data, not a device/platform measurement. Assume one Endpoint Tx Lane driving from the DUT toward TP1 at 5.0 GT/s, full swing, Non-Embedded Refclk, clean external clock, and no SRIS test. The chosen method is 1-port measurement with CC CDR. Assume the applicable compliance test load and the channel processing required for differential voltage.
Section 8.3.3.6 uses average transition eye amplitude at 0.5 UI over 500 Compliance Pattern repetitions at 2.5/5.0 GT/s. The following are idealized representative levels under that assumption; they explain amplitudes without modeling edges, overshoot, or noise. UI (Unit Interval) supplies the time unit for that sampling location.
| Complementary representative state | D+ (mV) | D− (mV) | VDIFF (mV) | VCM (mV) |
|---|---|---|---|---|
| H | 825 | 375 | +450 | 600 |
| L | 375 | 825 | −450 | 600 |
State H gives 825 − 375 = +450 mV; state L gives 375 − 825 = −450 mV. Differential peak-to-peak is therefore +450 − (−450) = 900 mVPP. Each individual conductor varies from 375 to 825 mV, only 450 mVPP single-ended. Both states give 600 mV common mode, an average potential rather than differential swing.
Follow Note 3 back to the method
In Table 8-6 choose VTX-DIFF-PP and the 5.0 GT/s column. Full-swing differential peak-to-peak voltage is 800–1000 mVPP. Note 3 points to §§8.3.3.6 / 8.3.3.7. Compare 900 mVPP from this case, rather than the 450 mVPP of D+ alone.
Under the stated measurement assumptions, that one swing result is in range. Jitter, common-mode noise, equalization, and other requirements need their own measurements. Two representative levels yielding 600 mV do not prove that a complete waveform has no AC common-mode noise.
Reduced-swing operation selects the separate VTX-DIFF-PP-LOW row. Both rows have a 1000 mVPP maximum in this edition, but different minima. A copied upper limit loses that mode distinction.
Base 6.0 §8.3.3.6 Method for Measuring VTX-DIFF-PP at 2.5 GT/s and 5.0 GT/s (p.1326); Table 8-6 Data Rate Dependent Transmitter Parameters, differential-swing rows (p.1348), Note 3 (p.1351).
Change methods when the rate and preset change
At 2.5/5.0 GT/s Tx equalization is de-emphasis, measured using the specified transition/non-transition average eye-amplitude ratio in §§8.3.3.1 / 8.3.3.4. Higher rates use coefficients and presets (predefined equalization combinations). Two representative levels from the preceding case are not a complete preset test.
For swing at 8.0/16.0/32.0/64.0 GT/s, §8.3.3.7 sets the applicable precursor/postcursor coefficients to zero and uses a low-frequency Compliance Pattern segment: 64 zeros then 64 ones at 8.0/16.0/32.0 GT/s, or 64 PAM4 level-0 then 64 level-3 symbols at 64.0 GT/s. Measure the specified late portion of each half-cycle and average 500 repetitions.
- PAM4
- Pulse Amplitude Modulation with 4 levels
For the preset itself, Figure 8-7 compares measured equalized output with a reconstruction made by applying coefficients to measured unequalized output, finding the best fit. Table 8-1 applies to 8.0/16.0/32.0 GT/s; Table 8-2 applies to 64.0 GT/s. Their ratios and tolerances define presets; coefficient magnitude is not output-voltage magnitude.
This connects to Chapter 19: the Link exchanges setting requests, while this chapter checks the resulting output. A requested setting, finished training, and a passed electrical requirement are separate observations.
Base 6.0 §§8.3.3.1–8.3.3.3 (pp.1321–1323); Tables 8-1 / 8-2 (pp.1324–1325); §§8.3.3.4–8.3.3.7 and Figure 8-7 Methodology for measuring Tx equalization coefficients and presets (pp.1325–1326).
Use the measured jitter quantity to select the pattern
Jitter (timing variation of edges or pulse widths) depends on pattern, equalization, and processing. Start with §8.3.5 before selecting a Table 8-6 parameter row.
| Rate and measured quantity | Pattern in §8.3.5 | Tx equalization condition |
|---|---|---|
| 2.5 / 5.0 GT/s jitter | Compliance Pattern, with specified zero-crossing treatment | Use the applicable rate-specific de-emphasis setting |
| 8.0 / 16.0 GT/s jitter | Compliance Pattern, with specified zero-crossing treatment | The preset yielding the lowest jitter should be selected |
| 32.0 GT/s jitter | Jitter Measurement Pattern | Must use no Tx equalization |
| 64.0 GT/s uncorrelated total jitter and deterministic jitter | Jitter Measurement Pattern, all twelve transitions between four PAM4 levels | Must use no Tx equalization |
| 64.0 GT/s uncorrelated total pulse width jitter and deterministic pulse width jitter | High Swing Toggle Pattern, transitions between levels 0 and 3 | Must use no Tx equalization |
- PAM4
- Pulse Amplitude Modulation with 4 levels
Tx jitter measurements at 32.0 and 64.0 GT/s require at least 50 GHz oscilloscope bandwidth. At 64.0 GT/s the specified fourth-order Bessel-Thomson filter, down 3 dB at 33 GHz, is recommended. Preserve the difference between a requirement and a recommendation.
Section 8.3.5 requires other PCIe Lanes to transmit Compliance Pattern while measuring one Tx Lane, to capture die/package crosstalk. The DUT must also drive as many outputs as normal system operation would use. Follow these task-specific conditions rather than treating §8.3.1's general environment introduction as the complete procedure.
Finally check the reference plane for the actual item. Table 8-6 explicitly says that VTX-AC-CM-PP and VTX-AC-CM-PP-filtered noise analysis is done without de-embedding. These common-mode voltage parameters are not jitter, and are an exception to the general voltage-processing rule. A report saying “everything referred to pins” still needs a row-by-row applicability check.
Base 6.0 §8.3.5 Tx Jitter Parameters (p.1336), §§8.3.5.1–8.3.5.2 (pp.1336–1338); Table 8-6 common-mode rows and notes (p.1350). This is a reading guide, not the full compliance procedure.
Edition and sources
PCI Express Base Specification Revision 6.0 (6.0-1.0-PUB) is the authority. Printed and PDF-viewer page numbers match at these locations. Idealized levels and measurement assumptions are marked beside the case; they are not device measurements or certification.
Reading locations and purpose
- §8.3.1, Figures 8-1 / 8-2 (pp.1318–1319); §8.3.1.1 (pp.1319–1320): test points, Breakout/Replica Channels, and reference plane.
- §8.3.2 Voltage Level Definitions, Equations 8-1 / 8-2 (p.1320); Figure 8-3 (p.1321): single-ended, differential, and common mode.
- §8.3.3 Tx Voltage Parameters and §§8.3.3.1–8.3.3.7 (pp.1321–1326); Tables 8-1 / 8-2, Figure 8-7: rate-specific swing, equalization, and preset methods.
- §8.3.5 Tx Jitter Parameters and §§8.3.5.1–8.3.5.5 (pp.1336–1338), Table 8-5 (p.1338): patterns, environment, clock sampling, and processing. Full PLL/transport-delay definitions follow the table into the relevant Refclk section and §8.6.6; their algorithms are not expanded here.
- §8.3.6 Data Rate Dependent Parameters, Table 8-6 (p.1347 onward): this case uses differential swing on p.1348 and Note 3 on p.1351; AC common-mode rows on p.1350 illustrate the no-de-embedding exception.
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