NVMe scenarios and source figures: lookup routes, field reasoning, worked answers and precise specification locations.
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NVMe Figures and Scenarios 05 · Features, Power, Performance, and Resources
NVM Express Base 2.4NVM Command Set 1.3NVMe over PCIe Transport 1.4
LOOKUP · FIELD INTERPRETATION · SOURCE LOCATIONS
NVMe Figures and Scenarios 05 · Features, Power, Performance, and Resources
Separate support, current, default and saved values before interpreting individual features. Power latency, scheduling weights, queue counts and reclamation resources use different units.
Follow a worked scenario through the specification
The returned data below are hypothetical. Start with the need and assumptions, follow the reading route to the relevant fields, then work through the interpretation. Explanations are visible; detailed sources can be expanded.
EXERCISE 01Why can a successful Get Features leave the current value unknown?
A tool displays DW0=5 as a feature’s current setting. Which interpretation layer did it miss?
Hypothetical observations and assumptions
- The controller supports Save/Select; SEL=3 targets a valid FID; CQE reports success and DW0=00000005h.
- Current, default and saved values have not been retrieved.
Which figures connect this scenario?
This is a specification reading route. The scenario separately explains action order and wait conditions.
- Read the request selectors
FID selects the feature and SEL selects the response kind; retain both to select the correct DW0 format.
Base 2.4 · Figure 198 - Decode the SEL=3 capability response
This figure defines CHANG, NSSPEC and SVBL in DW0 for SEL=3; decode 00000005h using that format.
Base 2.4 · Figure 201 - Proceed to the feature value
Find the FID’s own definition in the feature list, then retrieve its current value using SEL=0.
Base 2.4 · Figure 466 Base 2.4 · Figure 198
Follow the field interpretation
Lookup sequence: Retain FID/SEL/NSID from the request → interpret SEL=3 capabilities → query the same FID and correct target with SEL=0 for the current value.
- NSID
- Namespace Identifier
Step 1Five is binary 101: CHANG=1, NSSPEC=0, SVBL=1. This reports changeable attributes, non-namespace-specific scope and saveability, not a current value of five or proof of enablement.
Step 2SEL=0, 1 and 2 retrieve Current, Default and Saved respectively; they can differ. NSSPEC=0 also does not by itself establish controller-only scope; the feature definition determines that.
Step 3If a report retains DW0 but discards SEL, the meaning cannot be reliably reconstructed. Features with a data buffer also require that buffer; successful completion does not mean DW0 contains the complete response.
Detailed source locations
- Base 2.4 · §5.2.12 · Figure 198 · Get Features – Command Dword 10 · Printed pages 209–210 · PDF 235–236
- Base 2.4 · §5.2.12 · Figure 201 · Completion Queue Entry Dword 0 when Select is set to 11b · Printed pages 212 · PDF 238
- Base 2.4 · §5.2.30 · Figure 466 · Set Features – Feature Identifiers · Printed pages 457–459 · PDF 483–485
Continue with the other scenarios
EXERCISE 02How many queues follow from a request for sixteen?
A driver requests sixteen SQs and sixteen CQs, then creates QIDs 1 through 16. Does the response allow that?
Hypothetical observations and assumptions
- Set Features FID=07h requests NSQR=15 and NCQR=15; successful DW0=00030007h.
- CAP.MQES=1023; no Create I/O CQ/SQ commands have been issued.
Follow the field interpretation
Lookup sequence: Decode NCQA/NSQA in the FID=07h completion; read CAP.MQES separately before planning queue creation and depths.
Step 1DW0 has upper half three and lower half seven, allocating four CQs and eight SQs. A request for sixteen is not an allocation of sixteen; the response governs the result.
Step 2MQES=1023 allows up to 1024 entries per I/O queue, distinct from the number of queues. Multiple SQs may share a CQ under valid configuration, so the allocated counts need not match.
- CQ
- Completion Queue
Step 3Resources have been allocated, but queues do not yet exist. Establish an appropriate CQ before its SQ and verify each Create completion. Queue counts also do not directly specify MSI-X vector counts.
- CQ
- Completion Queue
- SQ
- Submission Queue
- MSI-X
- Message Signaled Interrupts Extension
Detailed source locations
- Base 2.4 · §5.2.30.1.5 · Figure 472 · Number of Queues – Command Dword 11 · Printed pages 465 · PDF 491
- Base 2.4 · §5.2.30.1.5 · Figure 473 · Number of Queues – Completion Queue Entry Dword 0 · Printed pages 466 · PDF 492
- Base 2.4 · §3.1.4.1 · Figure 36 · Offset 0h: CAP – Controller Capabilities · Printed pages 55–58 · PDF 81–84
EXERCISE 03What do two APST transitions imply after 700 ms idle?
- APST
- Autonomous Power State Transition
You need to explain the autonomous power path, not merely list the lowest-power state. How do the entries define source states and timing?
Hypothetical observations and assumptions
- APSTE=1; PS0 entry: ITPT=100, ITPS=2; PS2 entry: ITPT=500, ITPS=3.
- PS2 and PS3 are supported non-operational states; other relevant entries are disabled. Start in PS0 with 700 ms of uninterrupted idle.
Follow the field interpretation
Lookup sequence: Identify CNS=01h for APST capability and power-state descriptors → Get Features FID=0Ch, SEL=0 for both APSTE and the full APST buffer.
- APST
- Autonomous Power State Transition
Step 1The entry index selects the source; ITPS selects the destination. The path is PS0 → after its 100 ms idle threshold, PS2 → after the 500 ms threshold in PS2, PS3. The second timer is not simply counted from the initial PS0 idle instant.
Step 2Ignoring transition time for illustration, 700 ms allows the two thresholds to be reached in sequence. This timeline is not a measurement of the current state: actual transition time and controller behavior matter, and the table is configuration evidence.
Step 3To assess the next I/O’s exit cost, inspect the destination descriptor’s EXLAT. Zero means unreported, not zero latency. Work that interrupts idle also invalidates this uninterrupted-idle timeline.
| Source entry | Condition | Destination state |
|---|---|---|
| PS0 | Reach the 100 ms idle threshold in PS0 | PS2 |
| PS2 | Reach the 500 ms idle threshold in PS2 | PS3 |
Detailed source locations
- Base 2.4 · §5.2.30.1.7 · Figure 475 · Autonomous Power State Transition – Command Dword 11 · Printed pages 468 · PDF 494
- Base 2.4 · §5.2.30.1.7 · Figure 477 · Autonomous Power State Transition Data Structure Entry · Printed pages 469 · PDF 495
- Base 2.4 · §5.2.14.2.1 · Figure 340 · Identify – Power State Descriptor Data Structure · Printed pages 384–386 · PDF 410–412
EXERCISE 04Does a slowdown at high temperature establish HCTM activity?
Performance falls while temperature is above TMT1. Which reports strengthen the thermal-management interpretation, and what remains unproven?
Hypothetical observations and assumptions
- Get Features FID=10h: TMT1=340 K, TMT2=350 K; Identify limits permit these settings.
- SMART composite temperature is 345 K; during the test, Thermal Management Temperature 1 Transition Count rises by one and Total Time by 20 seconds.
Follow the field interpretation
Lookup sequence: Identify CNS=01h for HCTM capability and valid temperature limits → Get Features FID=10h, SEL=0 → compare two LID=02h SMART samples.
Step 1345 K is about 71.85°C, between the configured thresholds. Confirm units for settings and measurements; Kelvin is not Celsius, and a feature threshold is not the current temperature.
Step 2The counter and time increases support stage-one host-controlled thermal management activity during the interval. This is stronger than a high-temperature snapshot, but remains interval evidence rather than per-I/O timing.
Step 3You can report that thermal management was active, but cannot attribute the entire slowdown to it. Align measurement intervals, workloads, power states and PCIe link observations to investigate contributions.
Detailed source locations
- Base 2.4 · §5.2.30.1.10 · Figure 482 · HCTM – Command Dword 11 · Printed pages 472 · PDF 498
- Base 2.4 · §5.2.13.1.3 · Figure 213 · SMART / Health Information Log Page · Printed pages 221–225 · PDF 247–251
- Base 2.4 · §5.2.14.2.1 · Figure 338 · Identify – Identify Controller Data Structure, I/O Command Set Independent · Printed pages 359–360 · PDF 385–386
EXERCISE 05Does an unchanged HMB address establish an intact return?
- HMB
- Host Memory Buffer
After reset, the host clears an HMB at the same address and declares MR=1. Is address equality enough?
- HMB
- Host Memory Buffer
Hypothetical observations and assumptions
- Descriptor address and total size match the previous allocation, but buffer contents have been cleared.
- The proposed Host Memory Buffer feature has EHM=1, MR=1. This exercise only interprets the trace; no setting is applied.
Follow the field interpretation
Lookup sequence: Identify CNS=01h for HMB capability; inspect FID=0Dh and retained descriptors/buffer records from before disablement.
Step 1MR=1 declares return of the previous HMB, requiring more than matching address and size: descriptors and buffer contents must also remain consistent. Clearing the buffer breaks that condition.
Step 2EHM=1 requests enablement but cannot validate MR. Observing an enabled feature cannot reconstruct whether the host preserved every byte; lifecycle and memory-management records are needed.
Step 3Newly allocated memory must follow the new-HMB configuration path rather than treating an identical address as preserved contents. Controller capability and host compliance require different evidence.
Detailed source locations
- Base 2.4 · §5.2.30.2.3 · Figure 545 · Host Memory Buffer – Command Dword 11 · Printed pages 516–517 · PDF 542–543
- Base 2.4 · §5.2.14.2.1 · Figure 338 · Identify – Identify Controller Data Structure, I/O Command Set Independent · Printed pages 357, 362 · PDF 383, 388
EXERCISE 06Do weights seven and three guarantee a two-to-one IOPS ratio?
Measured high- and low-priority IOPS do not match configured weights. Does that prove an arbitration defect?
Hypothetical observations and assumptions
- CC.AMS selects a supported weighted arbitration mode; FID=01h reports HPW=7, MPW=3, LPW=3, AB=2.
- High- and low-priority workloads use different I/O sizes and read/write mixes.
Follow the field interpretation
Lookup sequence: Read CAP and CC.AMS → Get Features FID=01h, SEL=0 → correlate SQ priorities and actual workloads.
- SQ
- Submission Queue
Step 1HPW=7 and LPW=3 encode per-round weights of eight and four commands. AB=2 instead encodes a burst of 2^2=4. Similar-looking numbers do not necessarily use the same encoding.
Step 2Weights describe command-service opportunities, not equal work for commands with different sizes and execution costs. Eight-to-four weights do not directly guarantee a steady two-to-one IOPS or bandwidth ratio.
Step 3Arbitration validation needs the mode, SQ priorities, pending work and observation interval, evaluated against the specified service rules. An application throughput chart alone does not establish a violation.
Detailed source locations
- Base 2.4 · §5.2.30.1.1 · Figure 467 · Arbitration & Command Processing – Command Dword 11 · Printed pages 460 · PDF 486
- Base 2.4 · §3.1.4.5 · Figure 41 · Offset 14h: CC – Controller Configuration · Printed pages 60–63 · PDF 86–89
- Base 2.4 · §3.1.4.1 · Figure 36 · Offset 0h: CAP – Controller Capabilities · Printed pages 55–58 · PDF 81–84
01Get Features – Command Dword 10
Base 2.4 · Figure 198 · Get Features – Command Dword 10
§5.2.12 · Printed pages 209–210 · PDF 235–236
01.1 · UseIf a returned feature value differs from the last write, first check SEL. Get Features does not always read the current setting.
01.2 · Fields and relationshipsFID bits 7:0 selects the feature. SEL bits 10:8 values 0/1/2/3 select Current, Default, Saved or Supported Capabilities. A saved-value request falls back to Default if saving is unsupported or no saved value exists.
01.3 · Interpretation and exampleDW0=4 with SEL=3 is a capability bitmap, not a current feature value of 4. Decode it through Figure 201 and retain SEL and the feature’s target when comparing settings.
Back to this volume’s figure index02Completion Queue Entry Dword 0 when Select is set to 11b
Base 2.4 · Figure 201 · Completion Queue Entry Dword 0 when Select is set to 11b
§5.2.12 · Printed pages 212 · PDF 238
02.1 · UseUse this table only for a Get Features SEL=3 response. It reports operations supported by a feature, not the current value returned by SEL=0.
02.2 · Fields and relationshipsDW0 bit 2 is CHANG, bit 1 NSSPEC and bit 0 SVBL. NSSPEC=0 does not by itself mean controller scope; consult the feature and effects log. CHANG=1 indicates changeable attributes, not reversibility of every entered state.
02.3 · Interpretation and exampleDW0=6 means changeable, namespace-specific and not saveable. If permanent write protection has already been entered, CHANG does not promise it can be undone.
Back to this volume’s figure index03Set Features – Command Dword 10
Base 2.4 · Figure 464 · Set Features – Command Dword 10
§5.2.30 · Printed pages 457 · PDF 483
03.1 · UseWhen a setting works immediately but differs after reset, check the save request and then the feature’s persistence rules.
03.2 · Fields and relationshipsFID occupies bits 7:0 and SV bit 31; bits 30:8 are reserved. SV=1 requests saved attributes across all power states and resets. An unsaveable FID returns Feature Identifier Not Saveable.
03.3 · Interpretation and exampleSV=0 does not mean every state must disappear on the next reset. Some features intrinsically retain particular states. Saveability and persistence are separate questions.
Back to this volume’s figure index04Set Features – Feature Identifiers
Base 2.4 · Figure 466 · Set Features – Feature Identifiers
§5.2.30 · Printed pages 457–459 · PDF 483–485
04.1 · UseStart here when you have only an FID or need its scope and data-buffer requirement. Rows referring to NVM delegate the definition rather than denoting an inactive FID.
04.2 · Fields and relationshipsColumns cover current-setting persistence, data-buffer usage, name and scope. The persistence-column footnote limits its interpretation to unsaveable features; it does not override Saved-value behavior for saveable ones.
04.3 · Interpretation and exampleAPST FID=0Ch uses a data buffer of per-state entries; Power Management FID=02h mainly uses CDW11. Capturing CDW11 without the APST table cannot reconstruct that configuration.
Back to this volume’s figure index05Identify – Power State Descriptor Data Structure
Base 2.4 · Figure 340 · Identify – Power State Descriptor Data Structure
§5.2.14.2.1 · Printed pages 384–386 · PDF 410–412
05.1 · UseInspect each 32-byte descriptor when comparing power states or investigating wake latency. State numbers are selectors, not direct power or performance rankings.
05.2 · Fields and relationshipsNOPS bit 25 distinguishes I/O processing. MP bits 15:0 and MXPS bit 24 jointly encode power. ENLAT bits 63:32/EXLAT bits 95:64 use microseconds. IDLP/IPS describes idle power; RRT/RRL/RWT/RWL are relative rankings. Later fields include active power, power-loss timings and bandwidth.
05.3 · Interpretation and exampleMP=350 with MXPS=0 means 3.50 W; MXPS=1 means 0.035 W. EXLAT=0 means unreported, not zero latency. Check NOPS and valid power/latency values before selecting an APST destination.
Back to this volume’s figure index06Arbitration & Command Processing – Command Dword 11
Base 2.4 · Figure 467 · Arbitration & Command Processing – Command Dword 11
§5.2.30.1.1 · Printed pages 460 · PDF 486
06.1 · UseUse this table for SQ priority and command-fetch behavior. Weights do not guarantee a fixed application IOPS ratio; arbitration mode and workload still matter.
06.2 · Fields and relationshipsHPW bits 31:24, MPW bits 23:16 and LPW bits 15:8 encode per-round class command counts minus one. AB bits 2:0 limits commands fetched at once from one SQ as 2^AB, except AB=7 means unlimited.
06.3 · Interpretation and exampleHPW=3 means four commands while AB=3 means a burst of eight. Identical raw values use different encodings. Confirm CC.AMS before interpreting priority weights.
Back to this volume’s figure index07Power Management – Command Dword 11
Base 2.4 · Figure 468 · Power Management – Command Dword 11
§5.2.30.1.2 · Printed pages 461 · PDF 487
07.1 · UseThis CDW11 defines an explicit host-requested power-state transition. It is separate from APST; PS alone does not reconstruct autonomous transitions.
07.2 · Fields and relationshipsPS bits 4:0 selects a state, WH bits 7:5 supplies a workload hint, and IIELL bits 31:16 uses 100-microsecond units for supported idle-exit limits on operational states. IIELLSS determines its scope.
07.3 · Interpretation and exampleIIELL=5 means 500 microseconds, not 5 ms. With the capability supported, a nonzero IIELL for a non-operational state causes Invalid Field in Command. Identify the state type through its descriptor first.
Back to this volume’s figure index08Volatile Write Cache – Command Dword 11
Base 2.4 · Figure 471 · Volatile Write Cache – Command Dword 11
§5.2.30.1.4 · Printed pages 464–465 · PDF 490–491
08.1 · UseInspect WCE with cache presence and command FUA when assessing whether a Write completion may depend on volatile cache. WCE is not the hardware-presence capability.
08.2 · Fields and relationshipsCDW11 bit 0 enables/disables the cache; bits 31:1 are reserved. Presence also depends on Identify and namespace/FDP configuration. Flush and FUA have their own nonvolatile requirements.
- FDP
- Flexible Data Placement
08.3 · Interpretation and exampleWCE=1 does not prove that a particular completed Write exists only in cache: the command may have FUA=1. Preserve capability, WCE and command fields when investigating retention.
Back to this volume’s figure index09Number of Queues – Command Dword 11
Base 2.4 · Figure 472 · Number of Queues – Command Dword 11
§5.2.30.1.5 · Printed pages 465 · PDF 491
09.1 · UseUse this table for requested I/O queue allocation during initialization. Counts exclude Admin queues and do not describe individual queue depth.
09.2 · Fields and relationshipsNSQR bits 15:0 requests SQs and NCQR bits 31:16 CQs, both minus-one encoded with maximum raw value FFFEh. Configure before creating I/O queues; actual allocation is returned in CQE DW0.
- CQE
- Completion Queue Entry
09.3 · Interpretation and exampleEight SQs and four CQs use CDW11=00030007h. Do not create queues solely from the requested counts; inspect the actual result in Figure 473.
Back to this volume’s figure index10Number of Queues – Completion Queue Entry Dword 0
Base 2.4 · Figure 473 · Number of Queues – Completion Queue Entry Dword 0
§5.2.30.1.5 · Printed pages 466 · PDF 492
10.1 · UseDecode the Number of Queues completion here to learn the actual I/O queue resources allocated. Requested and allocated counts can differ.
10.2 · Fields and relationshipsDW0.NSQA bits 15:0 and NCQA bits 31:16 encode actual SQ/CQ counts minus one. This is neither a queue-ID list nor proof that Create commands have established those queues.
10.3 · Interpretation and exampleDW0=00010003h means four SQs and two CQs. Even after requesting eight and four, use the response for subsequent creation. Allocation and queue creation are separate steps.
- CQE
- Completion Queue Entry
11Autonomous Power State Transition – Command Dword 11
Base 2.4 · Figure 475 · Autonomous Power State Transition – Command Dword 11
§5.2.30.1.7 · Printed pages 468 · PDF 494
11.1 · UseIf an idle-transition table produces no expected power behavior, check APSTE first. This figure defines only the global switch, not per-state delays.
11.2 · Fields and relationshipsCDW11 bit 0 enables APST when one and disables it when zero, the default. Other bits are reserved. Per-source-state timing and destination settings reside in the APST data structure.
11.3 · Interpretation and exampleAPSTE=1 does not immediately select the lowest-power state. The source entry needs nonzero ITPT and the continuous-idle condition must be met. Capture both enablement and the relevant entry.
Back to this volume’s figure index12Autonomous Power State Transition Data Structure Entry
Base 2.4 · Figure 477 · Autonomous Power State Transition Data Structure Entry
§5.2.30.1.7 · Printed pages 469 · PDF 495
12.1 · UseDecode each eight-byte source-state entry here. Its array index selects the source; ITPS selects the destination. They are not interchangeable.
12.2 · Fields and relationshipsITPT bits 31:8 is the continuous-idle threshold in milliseconds; zero disables that source entry. ITPS bits 7:3 selects a non-operational destination when ITPT is nonzero. Upper 32 bits and low 3 bits are reserved.
12.3 · Interpretation and exampleFor a PS0 entry with ITPT=2000 and ITPS=3, the low Dword is(2000<<8)|(3<<3)=0007D018h. The rule can transition from PS0 to PS3 after more than 2000 ms continuously idle in PS0, not after first entering PS3.
Back to this volume’s figure index13HCTM – Command Dword 11
Base 2.4 · Figure 482 · HCTM – Command Dword 11
§5.2.30.1.10 · Printed pages 472 · PDF 498
13.1 · UseInspect Host Controlled Thermal Management thresholds when performance drops with temperature. They are host-selected controls, not current SMART readings.
13.2 · Fields and relationshipsTMT1 bits 31:16 selects the lighter threshold and TMT2 bits 15:0 the heavier one, both in Kelvin; zero disables that part. Nonzero values must fit Identify limits, and nonzero TMT2 must exceed TMT1.
13.3 · Interpretation and exampleTMT1=343 and TMT2=353 are about 69.85°C and 79.85°C, not 343°C/353°C. Use SMART transition counts and total times to investigate actual activity.
Back to this volume’s figure index14Interrupt Coalescing – Command Dword 11
Base 2.4 · Figure 543 · Interrupt Coalescing – Command Dword 11
§5.2.30.2.1 · Printed pages 515 · PDF 541
14.1 · UseCheck coalescing when CQ data exists before its interrupt arrives. It aggregates interrupts without changing command status in CQEs.
14.2 · Fields and relationshipsTIME bits 15:8 uses 100-microsecond units, zero meaning no delay. THR bits 7:0 is the recommended completion threshold minus one. Either field zero implicitly disables coalescing. It applies to I/O queues, not Admin CQ, with additional per-vector configuration.
14.3 · Interpretation and exampleTIME=5/THR=7 specifies recommendations of 500 microseconds and eight entries, not a mandatory 500-microsecond delay per I/O. CQ head updates can restart aggregation conditions, so TIME is not an end-to-end latency bound.
Back to this volume’s figure index15Host Memory Buffer – Command Dword 11
Base 2.4 · Figure 545 · Host Memory Buffer – Command Dword 11
§5.2.30.2.3 · Printed pages 516–517 · PDF 542–543
15.1 · UseWhen re-enabling Host Memory Buffer after reset or power changes, inspect MR/EHM so newly allocated memory is not represented as an intact return. HMB is host memory supplied for controller use.
15.2 · Fields and relationshipsEHM bit 0 enables the HMB when set, MR bit 1 declares return of the prior HMB, and HMNARE bit 2 restricts supported non-operational access with Admin-related exceptions. Bit 3 must be zero. MR=1 requires identical size, descriptor address/content and buffer content.
15.3 · Interpretation and exampleIf reallocation cleared the buffer, the same physical address does not justify MR=1. With EHM=0, CDW12–15 are ignored, so their bytes do not establish an enabled allocation.
Back to this volume’s figure index16FDP Configuration Descriptor
- FDP
- Flexible Data Placement
Base 2.4 · Figure 294 · FDP Configuration Descriptor
§5.2.13.1.29 · Printed pages 293–295 · PDF 319–321
16.1 · UseCheck the active FDP configuration before decoding resource counts or Placement Identifiers. RGIF determines the split between Reclaim Group and Placement Handle in a PID.
16.2 · Fields and relationshipsDSZE bytes 1:0 gives descriptor size. FDPA byte 2 contains FDPCV validity, FDPVWC and RGIF. NRG bytes 7:4/NRUH bytes 9:8 are direct counts; MAXPIDS bytes 11:10 is minus-one encoded. RUNS bytes 23:16 counts nominal bytes; ERUTL bytes 27:24 seconds, with zero unreported.
16.3 · Interpretation and exampleNRUH=4 means four handle descriptors, not five; MAXPIDS=3 corresponds to four placement identifiers. Vendor bytes and padding may follow the list, so use DSZE to find the next configuration.
Back to this volume’s figure index17Reclaim Unit Handle Status Descriptor
NVM Command Set 1.3 · Figure 21 · Reclaim Unit Handle Status Descriptor
§3.2.1.1 · Printed pages 26 · PDF 26
17.1 · UseUse this NVM-specific status descriptor to inspect currently writable capacity in the Reclaim Unit referenced by a placement. Nominal capacity is not a substitute for this snapshot.
17.2 · Fields and relationshipsPID bytes 1:0 and RUHID bytes 3:2 identify placement and handle. EARUTR bytes 7:4 estimates remaining seconds, with zero unreported. RUAMW bytes 15:8 counts currently writable logical blocks. The remaining 16 bytes are reserved.
17.3 · Interpretation and exampleRUAMW=1000 with 4 KiB blocks means 4,096,000 bytes in block units and can differ in either direction from RUNS nominal capacity. EARUTR=0 does not mean immediate expiration.
Back to this volume’s figure index
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