PCIe Chapter 8: Link Training and Reliable Delivery

Link training and Function readiness are separate stages

The Physical Layer Link Training and Status State Machine (LTSSM) establishes receive synchronization, Lane relationships, and Link width. The main initial path is Detect, Polling, Configuration, and L0. Configuration here is a training state, not Base Address Register (BAR) programming. Recovery restores synchronization or changes speed. Its entry reason and subsequent state explain which operation is taking place.

During initial Link establishment, once the Physical Layer is operational, the Data Link Layer still completes applicable Feature Exchange and Virtual Channel 0 (VC0, the default transmission resource group) Flow Control initialization before DL_Active (the active data-link state). Configuration readiness, BAR (device-resource base address) setup, and Direct Memory Access (DMA) preparation are separate conditions. Data Link Layer Packets (DLLPs) remain between adjacent Link partners; Transaction Layer Packets (TLPs) can traverse Switches to another component.

BAR

Base Address Register

Read supported speeds, the target, and current speed

Figure 7-38/Table 7-35: (0x0180001E & 0xFE) >> 1 = 0x0F, so both ends support 2.5, 5, 8, and 16 GT/s. Figure 7-39/Table 7-36: Downstream Port Target=3 limits normal operation to 8 GT/s. Figure 7-29/Table 7-26: Current=3 and Width=4 give 8 GT/s ×4, consistent with that limit and the Endpoint width. Maximum implemented width also need not equal physically wired width.

The example Downstream Port supports Link Active reporting, making Status bit 13=1 evidence of DL_Active (the active data-link state). The Endpoint does not implement that reporting; its zero is not evidence of disconnection. Current Speed/Width are undefined when the Link is not up. Retrain Link triggers on a write of 1 and always reads zero; inspect applicable Training/Active status and final Speed/Width instead. Link Training is Reserved in Endpoints.

Use LinkUp to decide whether Recovery requires reinitialization

A Link already in DL_Active can pass through Recovery and return to L0 while retaining its data-link state. Find the observed path in Figure 4-48, then read Table 4-48: both Recovery and L0 report LinkUp=1. LinkUp is the Physical Layer indication to the Data Link Layer. Under §3.2.1, DL_Active transitions to DL_Inactive when Physical LinkUp becomes zero. This condition connects the two state machines.

Finally, compare software-visible status in Table 7-26. Data Link Layer Link Active is 1 only in DL_Active, and only a Port supporting this reporting provides a meaningful value. The example uses the reporting-capable Downstream Port. Reading 1 before and after the event does not reveal a transition between those samples. DL_Up in Figure 3-2 is a separate status output: DL_Init already reports DL_Up during FC_INIT2, while TLP transmission on that VC must still wait for initialization to complete.

TLP

Transaction Layer Packet

VC

Virtual Channel

Connect Figure 4-48, Table 4-48, and Figure 3-2 to establish whether reinitialization is required. Control writes, errors, and packet records are then needed to explain the Recovery trigger and the outcome of each Transaction.

Credits manage space; replay protects this hop

In Non-Flit Mode, each Virtual Channel separately tracks Header and Data credits for Posted, Non-Posted, and Completion traffic: six classes. One Data credit represents 16 bytes; Headers are accounted separately. An authored VC0 (default Virtual Channel) example starts with finite, unscaled available Posted Header (PH)=2 and Posted Data (PD)=5, without competing traffic. A 64-byte Memory Write (MWr) consumes 1 PH (Posted Header) and 4 PD (Posted Data), leaving 1/1. A following 32-byte MWr (Memory Write) requires 1/2 and waits until available PD increases by 1. This is an available-credit ledger, not a standard software-readable Register or a minimum initial advertisement.

A 256-byte Memory Read (MRd) request has no data Payload and needs only one Non-Posted Header (NPH) credit; its return traffic consumes Completion credits in the opposite direction. Sufficient credits do not guarantee immediate scheduling: ordering and arbitration still apply.

Non-Flit sequence numbers, LCRC (Link Cyclic Redundancy Check, the error-checking code), ACK/NAK (positive/negative acknowledgement), and replay provide adjacent-Link reliability. The transmitter retains copies; a NAK (negative acknowledgement) or acknowledgement timeout can cause replay. The receiver handles duplicate copies, and the Transaction Layer does not charge new credits again for the same TLP (Transaction Layer Packet). An ACK (positive acknowledgement) on one hop is neither a transaction Completion nor device-work completion. Posted MWr has no ordinary Completion but still receives Link-level protection.

Flit Mode uses a fixed transport unit

64 GT/s uses Flit Mode, which can also operate at lower rates. A 256-byte Flit contains 236 bytes for TLPs, 6 for Data Link Layer Payload (DLP), 8 for Cyclic Redundancy Check (CRC), and 6 for Error Correction Code (ECC). TLPs can span Flits, and multiple TLPs can share one Flit; the TLP region is not all application data. Replay operates at Flit granularity. Forward Error Correction (FEC) neither eliminates replay nor corrects every possible error.

Check Flit Mode Supported in PCI Express Capabilities before interpreting Downstream Port Link Status 2. A projection containing only Presence and the Flit bit of 0x4400 means Presence=100b and Flit=1: Link up, with no Device Readiness Status (DRS) received yet. A projection of 0x3400 means negotiation has completed but the Data Link Layer is not active. These are field projections, not full dumps; the Flit bit is meaningful only for Presence=011b, 100b, or 101b.

Follow a different packet through the same Link