PCIe Chapter 34: Readiness, Advanced Hot-Plug, and Platform Management

Interpret a device readiness notification

Section 6.22.1 defines the Configuration-Ready scope of DRS. After notification, indicated non-VF functions must not return RRS to configuration requests until another applicable event. Switch scope has explicit limits. In the author scenario, an applicable DRS lets configuration proceed; if it has not arrived, choose the applicable waiting procedure based on support. The §6.22 recommended DRS-only and hybrid procedures have different prerequisites.

DRS

Device Readiness Status

Handle queued function readiness

Root Ports/RCECs supporting FRS must implement FRS Queueing. Messages are queued in arrival order, with the oldest visible and removed by the defined write. On a full queue, discard the new message, set overflow, and preserve existing entries. Overflow is not replacement with a fresh snapshot.

FRS

Function Readiness Status

Connect hot-plug ownership and enclosure control

Reconnect Chapters 11–13 hot-plug, DPC, and ownership before reading Appendix I. Its recommended model checks owner/mechanism, presence, readiness, and interrupts; it recommends DPC without making the full model mandatory. NPEM (Native PCIe Enclosure Management) supplies enclosure controls such as LEDs at a downstream port or endpoint, as Figures 6-35/6-36 show. SFI (System Firmware Intermediary) is a separate firmware event-intermediary mechanism.

DPC

Downstream Port Containment

Where does the wait begin after reset?

Identify the device-level or function-level event first. DRS reports device readiness; FRS reports readiness of specific functions. Check the scope of the message and whether a later applicable event occurred.

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Configuration-Ready concerns Configuration Requests; it does not itself establish BAR, driver, or internal device initialization. These examples are illustrative.

BAR

Base Address Register

Where does DRS end, and where can FRS begin?

Start with the common PCI-SIG Defined VDM format in §2.2.8.6.1, then select Figure 2-51 for Non-Flit Mode or Figure 2-52 for Flit Mode. DRS has no payload: Type is Msg, TC is 000b, Message Code is 7Fh, Vendor ID is 0001h, and Subtype is 08h; Attr and Tag are Reserved. Table 2-29 defines Routing 100b as local termination at the receiver.

TC

Traffic Class

Teaching scenario: an Endpoint Upstream Port sends DRS to the adjacent Root Port after the relevant non-VF Functions are Configuration-Ready. The DRS terminates at that receiving Port; it is not forwarded unchanged. Assume the Root Port supports FRS, DRS Signaling Control is set to DRS to FRS Signaling Enabled, and DRS Message Received transitions from 0 to 1 on receipt. Under §7.5.3.7 the Port must send a separate FRS with Reason 0001b. That FRS identifies the Downstream Port in Requester ID and uses Routing 000b toward the Root Complex. Selecting this signaling mode when FRS Supported is clear has undefined behavior.

Section 6.22.1 requires DRS for the applicable Ports supporting Flit Mode, but current speed or mode alone does not reveal the other endpoint's full capabilities. DRS has no enable/disable mechanism; DRS Signaling Control governs signaling after receipt. Receiver checks are independently optional and must not check Reserved bits. An implemented check that detects a violation reports Malformed TLP at the receiving Port. A Completer that does not implement the PCI-SIG Defined VDM silently discards it under the common rule.

TLP

Transaction Layer Packet

Who does the Requester ID identify in an FRS message?

In §2.2.8.6.3, choose Figure 2-53 for Non-Flit Mode or Figure 2-54 for Flit Mode and locate Requester ID and FRS Reason. Then read the reason definitions and §6.22.2 to determine the affected scope. FRS is a PCI-SIG Defined Vendor_Defined Type 1 Message without payload: Type is Msg, TC is 000b, and Subtype is 09h. Table 2-30 gives Message Code 7Fh and Routing 000b to the Root Complex. The shared PCI-SIG VDM rules in §2.2.8.6.1 set Vendor ID to 0001h; FRS declares Attr and Tag Reserved, so they are not indicators of the reason or target.

TC

Traffic Class

Reason 0011b reports that the identified Function completed FLR and is Configuration-Ready. For 1000b, Requester ID identifies a Physical Function (PF), and all its associated Virtual Functions (VFs) are Configuration-Ready. Reason 1001b means those VFs are disabled and the PF's SR-IOV structures may be accessed. Reason 0010b identifies a Function completing D3Hot to D0; whether it returns to D0uninitialized or D0active depends on No_Soft_Reset. For 0001b, the identified Downstream Port has received DRS with DRS to FRS Signaling Enabled; its readiness scope is defined in §6.22.1. Other reason values are Reserved.

FLR

Function Level Reset

SR-IOV

Single Root I/O Virtualization

Teaching assumption: an FRS identifies PF A and has Reason 1000b. It reports readiness for PF A's associated VFs, not those of another PF. Receiver checks of the message formation rules are independently optional; if an implemented check finds a violation, §2.2.8.6.3 specifies Malformed TLP reporting at the receiving Port. Reserved bits must not be checked. Under §2.2.8.6.1, a Completer that does not implement a PCI-SIG Defined VDM silently discards it; unsupported Type 1 handling is distinct from an implemented check detecting malformed content.

TLP

Transaction Layer Packet

Which event starts each timer?

The Readiness Time Reporting Extended Capability is optional. Find it via the capability list and use Figure 7-314 to locate the registers at capability-relative offsets +04h and +08h. Figures 7-317 and 7-318 and Tables 7-279 and 7-280 explain the fields and their applicability.

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Check Valid before using the values. When it is clear, time fields are undefined. Figure 7-315 gives Value × 32^Scale ns; Scale 6 and 7 are reserved. Cached values are usable only while the same device operates in the same manner.

FLR Time and DL_Up Time start at different events; adding them is not a general waiting procedure. Apply §7.9.16 when an applicable notification or another permitted wait completes earlier.

What remains known after FRS Queue overflow?

Teaching scenario: A Root Port queue is full with A and B in order when message C arrives. Section 6.22.3 preserves A and B, discards C, and sets FRS Message Overflow. Reading the Queue Register shows A; writing it removes the oldest entry, allowing B to be read next.

A 0-to-1 transition of FRS Message Received or Overflow generates an interrupt if enabled. Overflow indicates a message was not queued, so the retained entries cannot reconstruct C. Reset empties the queue; a Root Port also empties its queue when the Link goes DL_Down. An RCEC queue contains messages generated by the RCEC or associated RCiEPs.

How do readiness, enclosure indicators, and hot-plug management connect?

Appendix I is a non-normative reference model. First identify OS and system firmware ownership, then select Hot-Plug Surprise or Downstream Port Containment (DPC); the model recommends DPC where available but is not a universal required platform sequence.

NPEM handles enclosure indicators separately. Figures 6-35 and 6-36 show the capability in a Downstream Port or at the SSD, and Figure 6-37 connects an NPEM Control write with command completion. The Base specification leaves enclosure wiring, LED count, and blink patterns outside its scope. An indicator alone does not establish Configuration-Ready.

NPEM

Native PCIe Enclosure Management

Keep AF within its applicability

AF (Conventional PCI Advanced Features) applies to qualifying conventional PCI devices integrated into a Root Complex. Section 6.29 limits its FLR/Transactions Pending applicability. Ordinary PCIe functions use their own capability and Chapter 9 reset rules; similar names do not imply identical registers or scope.

Edition and sources

This chapter uses PCI Express Base Specification Revision 6.0 (6.0-1.0-PUB). Document and PDF page numbers match. Example configurations and values are author assumptions, not device measurements.