PCIe Chapter 33: Protocol Multiplexing and Alternate Protocols

Separate PCIe traffic and PMUX resources

Figure G-2 shows separate PCIe and PMUX (Protocol Multiplexing) transmit queues sharing an arbiter and Link; the receiver demultiplexes the packets. Figure G-3 traces a PMUX Packet through a protocol-specific layer, simplified Data Link Layer and Physical Layer.

A PMUX Packet has its own LCRC (Link Cyclic Redundancy Check), but does not use PCIe TLP Sequence Numbers, Ack/Nak or TLP Credits. Its 12-bit Metadata is protocol-specific. Confirmation, retries, flow control and cross-component addressing need the multiplexed protocol's own definition.

TLP

Transaction Layer Packet

This lesson follows Base 6.0 Appendix G at 2.5–32.0 GT/s; its PMUX Supported Link Speeds field does not define a 64.0 GT/s support bit. Do not apply these packet formats directly to 64.0 GT/s Flit Mode.

PCIe Base 6.0 Appendix G, Figures G-1–G-3, printed/PDF pp.1561–1563; §G.5.2, Table G-7, pp.1575–1576.

Map both ends of Channel 0 to the same protocol

Simulated data: a Link runs at 16.0 GT/s x4 between a Downstream Port and Upstream Port Function 0. Both have PMUX Extended Capability ID 001Ah, Version 1. At each capability base P, P+04h=00000C02h: Protocol Array Size=2 and PMUX supports 8.0 and 16.0 GT/s. The Links support those speeds; assume the protocol document permits the chosen speed and width.

Figure G-7 locates the Array; Figure G-12/Table G-10 assigns high 16 bits to Authority ID and low 16 bits to Protocol ID. Assume the same two protocols appear in different orders; the identifiers below are invented and carry no asserted vendor-specific meaning.

Write 1 and 2 respectively to Control P+08h bits 5:0. Both select Authority ID 1234h / Protocol ID 0001h; compare protocol compatibility rather than assuming matching array indices. Assignment 0 means no protocol, the Array starts at 1, and entry 00000000h is unimplemented. Array Size=0 is permitted and means the Port lists no supported PMUX protocols.

Assume both Status registers P+0Ch show Channel 0 Disabled: Link Speed, Link Width and Protocol Specific all clear and protocol-specific initialization has completed. Channel 0 then meets this example's transmission conditions. When Assignment=0, those bits also read zero, so zero status alone does not establish an enabled channel.

Both Link partners must support PMUX and each end must explicitly configure the Channel. Incompatible protocols configured for the same Channel yield undefined behavior. A disabled Channel cannot transmit PMUX Packets; received packets on a disabled Channel are silently ignored by a PMUX-capable Port.

PCIe Base 6.0 §§G.4–G.5.5, Figures G-7–G-12, Tables G-6–G-10, printed/PDF pp.1573–1580.

Distinguish Recovery, speed change and Reset

For the same Channel 0, Table G-1 says Recovery has no effect on PMUX. Still check for a separate DL_Down or speed change during the observed interval; a final L0 snapshot does not supply the full history.

If the Link moves to 32.0 GT/s, this example's PMUX Capability bit 12 is clear and does not support that speed. Channel 0 is disabled for speed and Status can indicate Disabled: Link Speed=1. Conversely, a PMUX-supported speed may still be unsupported by a particular protocol; consult that protocol's speed and width rules.

DL_Down, Hot Reset, PERST# or FLR to Upstream Port Function 0 disables all PMUX Channels on the Link; FLR to another Function has no such effect. After recovery, recheck both ends' support, protocol mapping, speed, width and Channel configuration, then perform any required protocol initialization.

FLR

Function Level Reset

PCIe Base 6.0 §G.1, Table G-1 PCI Express Attribute Impact on Protocol Multiplexing, printed/PDF pp.1563–1565; §G.5.4, Table G-9, pp.1578–1579.

Alternate Protocol uses a separate index and negotiation control

The Alternate Protocol Extended Capability is a separate discovery/negotiation interface. Locate ID 002Bh, Version 1, then use Figure 7-336 for Capability, Control and Data 1/2. It is permitted in a Downstream Port Function or Upstream Port Function 0. Its Index Select is not the PMUX Channel Assignment.

Simulated data: Downstream Port Alternate Protocol Capabilities=00000103h means Count=3 and Selective Enable Supported=1, so the Selective Enable Mask exists. Index 00h is PCIe. Assume Index 01h is disabled: Data 1 returns Vendor ID FFFFh and its Usage, Details and Data 2 values are undefined. Decode the remaining entry using its reported Vendor ID and the applicable protocol document; this does not establish that it is enabled or currently operating.

Count is the number of supported entries, not the current operating mode. Table 7-298 returns Vendor ID FFFFh for Index greater than or equal to Count; Table 7-297 makes writing Index greater than Count undefined. The example's normal entry indices are 00h–02h, not a fourth entry at 03h.

When Global Enable=1, the corresponding Selective Enable Mask bit is 1, and the entry is not disabled, the next negotiation may consider that protocol. Mask changes affect the next negotiation, not current Link operation. Upstream Ports hardwire Selective Enable Supported to zero.

PCIe Base 6.0 §§7.9.20–7.9.20.6, Figures 7-336–7-342, Tables 7-295–7-300, printed/PDF pp.1282–1286.

Edition and sources

This chapter uses PCI Express Base Specification Revision 6.0 (6.0-1.0-PUB). Document and PDF page numbers match. Example configurations and values are author assumptions, not device measurements.