PCIe Chapter 30: Root Complex Declarations, Identity, and Device Data

Distinguish type from an individual unit

Use Vendor/Device IDs from Chapter 3 for type identification, then supported Device Serial Number or product data for unit information. Table 7-222 defines the 64-bit serial field and byte mapping. VPD can provide part/serial information. Keep the source of each identifier rather than treating a type ID as a unique card identity.

VPD

Vital Product Data

Simulated data: if the Serial Number Register reads low DWORD 44332211h and high DWORD 88776655h, Table 7-222 maps the register bytes to EUI-64 as 11-22-33-44-55-66-77-88. These are invented bytes, not an assigned identifier. Byte order must be decoded from the table before comparing with another representation.

PCIe Base 6.0 §7.9.3.2, Figure 7-243/Table 7-222, printed/PDF pp.1206–1207.

Read a product name through the VPD interface

VPD (Vital Product Data) stores product and service information. Walk the ordinary Capability List, then use Figure 7-328 to locate Address at capability offset 02h and Data at 04h. VPD Address identifies a byte in the storage component; it is not a Configuration Space offset.

Simulated data: this Function's VPD storage is readable through at least 07h and starts with bytes 82 05 00 43 41 52 44 31. This is only a product-name example, not a complete VPD or checksum.

Table 7-289 requires a DWORD-aligned byte address. Table 7-290 places the byte at that address in Data's least-significant byte and requires Byte Enable 1111b. Read the first four bytes only after F=1, then start the second transfer. Writing Address or Data before a read completes, or requesting an address outside the storage range, has undefined behavior.

In Table 6-20, 82h is a Large Resource tag with item name 02h, the Identifier String. The next two bytes 05 00 give little-endian length 5. The five ASCII bytes 43 41 52 44 31 form CARD1. The remaining VPD, its end tag and VPD-R checksum require further reads.

For a write, first place four bytes in Data, then write Address and F=1 together and wait for hardware to clear F to 0. Writing Address or Data while the write is incomplete makes the storage result unpredictable. The device and platform define the writable area and maintenance procedure; stored VPD does not directly control device operations.

PCIe Base 6.0 §§7.9.18–7.9.18.2, Figures 7-328–7-330, Tables 7-289–7-290, printed/PDF pp.1274–1276; §6.27, Tables 6-19–6-21, pp.830–832.

Identify the defining vendor before decoding private data

Start with the correct Capability List and qualify the defining vendor, structure ID, revision and length:

For a VSEC (Vendor-Specific Extended Capability), the Function's Vendor ID identifies the defining vendor; an RCRB uses the Vendor ID in its RCRB Header. A DVSEC (Designated Vendor-Specific Extended Capability) has its own DVSEC Vendor ID. Base defines structure identification; the appropriate vendor definition is needed for the private register semantics.

PCIe Base 6.0 §§7.9.4–7.9.6.3, Figures 7-244–7-251, Tables 7-223–7-228, printed/PDF pp.1207–1212.

Interpret RCEC association for integrated endpoints

A Root Complex may expose an opaque model or visible logical components and RCRBs (Root Complex Register Blocks). Figure 6-11 illustrates one visible component; a Link Declaration describes software-visible relationships and does not by itself reveal all physical wiring.

An RCEC (Root Complex Event Collector) uses Endpoint Association to describe associated RCiEPs (Root Complex Integrated Endpoints). Figure 7-269 locates the bitmap; Capability Version 2 includes the additional Associated Bus Numbers Register.

Simulated data: an RCEC at Bus 10h, Device 2 reports Association Bitmap=00000024h. Bit 2 is required for the RCEC's own Device Number. If Device 5 on that same Bus is an RCiEP, bit 5 associates it with this RCEC. The bitmap indexes Device Numbers, not Function Numbers.

Assume Version 2 with RCEC Next Bus=20h and Last Bus=22h. The range can contain additional associated RCiEPs; Root Ports within it are not thereby associated, and the bus range does not indicate association with VFs. If all associated devices are on the RCEC's own Bus, Next Bus=FFh and Last Bus=00h. Association describes event collection; each Function's identity and resources still need their own records.

PCIe Base 6.0 §6.10, Figure 6-11, printed/PDF pp.748–749; §§7.9.10–7.9.10.3, Figures 7-269–7-271, Tables 7-241–7-242, pp.1227–1229.

Edition and sources

This chapter uses PCI Express Base Specification Revision 6.0 (6.0-1.0-PUB). Document and PDF page numbers match. Example configurations and values are author assumptions, not device measurements.