PCIe Chapter 28: ACS, Peer-to-Peer, and Multicast

Locate the ingress ACS controls before following A to B

A enters the Switch through DP1; normal address decoding selects DP2 toward B. DP1 is the Ingress Port and DP2 the candidate Egress Port. Read the ingress DP1 ACS (Access Control Services) controls for this P2P (Peer-to-Peer) Request.

Simulated data: UP0 has Port Number 0; DP1/DP2/DP3 have Numbers 1/2/3. A/B/C use Requester IDs 0300h/0400h/0500h. DP1 has Secondary and Subordinate Bus Number 03h, without FPB. B's BAR covers 90000000h–90000FFFh; C's covers A0000000h–A0000FFFh. Required resources, Windows, Memory Space Enable, Bus Master Enable and Link transport are ready. Packet examples use Non-Flit Mode, without Reset or Replay events.

FPB

Flattening Portal Bridge

BAR

Base Address Register

A issues a four-byte Memory Write to 90000500h with AT (Address Type)=00b. The AT definitions continue Chapter 27. This case follows route selection. A Posted Write has no ordinary Completion; observing its destination's internal write result requires further evidence.

Base 6.0 §§6.12–6.12.1.1, pp.751–755; address and Window routing: Chapter 5.

Connect capability, control and the destination vector bit

Walk the capability list for ID 000Dh, Version 1, and use Figure 7-131. With DP1's base A, A+04h is ACS Capability, A+06h ACS Control and A+08h the Egress Control Vector.

Capability 087Fh advertises the first seven controls, no ACS Enhanced Capability, and eight vector bits. Control 001Dh enables Source Validation, P2P Request Redirect, P2P Completion Redirect and Upstream Forwarding. Translation Blocking, P2P Egress Control and Direct Translated P2P are disabled.

For selective control toward B, use DP2's Port Number 2. Equation 7-4 gives offset 08h+(2 div 32)×4=08h, bit 2, mask 00000004h. The index is not B's Bus Number, Function Number or analyzer channel. Egress Control Enable determines whether that vector participates.

Vector Size 00h means 256 bits when Egress Control is supported. Without that capability, Size is undefined and the vector need not exist.

Base 6.0 §§7.7.11–7.7.11.4, Figures 7-131–7-135, Tables 7-116–7-119, Equation 7-4, pp.1083–1089.

Which settings change the route to the same address?

Source Validation accepts this example's Requester Bus 03h within DP1's 03h–03h aperture. RID 0600h would instead cause ACS Violation. This aperture check does not authenticate a process or authorize every data address.

RID

Routing ID, the packet routing identity

Enabled Translation Blocking rejects an upstream Memory Request whose AT is not the default 00b. It takes precedence over Upstream Forwarding and P2P mechanisms. After ingress checks, use Table 6-11.

Each row below is an independent snapshot, not a programming sequence. E is P2P Egress Control Enable, R P2P Request Redirect Enable, V the ingress vector's bit for DP2, D Direct Translated P2P Enable, and TB Translation Blocking Enable. Translated rows assume a valid translation and Write permission. The comparison enabling both Direct and Redirect also assumes the ordering preconditions in §6.12.6.2 are satisfied.

The normal case has E=0/R=1 and redirects toward the RC. With E=1/R=1/V=0, Table 6-11 instead requires direct routing; V=1 redirects. E=1/R=0/V=1 causes ACS Violation. Read R together with E and V.

For an applicable Memory Request with AT=10b and D=1, Direct Translated P2P overrides Request Redirect and Egress Control. However, TB=1 in the last row already requires ACS Violation; D does not override Translation Blocking. Direct routing still depends on valid routing and authorization.

Base 6.0 §6.12.1.1, pp.752–754; §6.12.3, Table 6-11, pp.757–758; Table 7-118, pp.1087–1088; §6.12.6.2, p.761.

Continue through the RC, return traffic and error handling

Return to Control 001Dh. Required ACS Upstream Forwarding along the redirection path must be effective, and the RC must implement Redirected Request Validation. Upstream Forwarding handles traffic that would otherwise return through the receiving Downstream Port's own egress; relevant handling is undefined when it is disabled. A single-Function Switch Upstream Port does not thereby require its own ACS Capability.

RC validation decides whether a Request is reflected Downstream or blocked as ACS Violation. Its algorithms and specific controls are platform defined. Root Port Redirect capability does not imply any level of RC P2P support. For the normal example, additionally assume RC validation permits reflection through the Root Port, Switch UP0 and DP2 toward B. Downstream Ports do not redirect that Downstream Request back Upstream. B's internal write result still needs observation.

Separately consider B's Completion for an earlier Memory Read from A. It enters DP2, so read DP2's Completion Redirect control. When enabled, a peer Completion with RO (Relaxed Ordering)=0 redirects Upstream; RO=1 routes normally. Request Redirect, Egress Control and Translation Blocking do not affect Completions.

Completion redirection prevents a direct non-RO Completion from effectively passing a redirected Posted Request. Mixed paths need §6.12.6's ordering analysis; fewer hops alone do not establish legality. Full Passing rules are in Chapter 15.

An ACS Violation on a Non-Posted Request requires a CA (Completer Abort) Completion; a Posted Write has no such ordinary reply. The handling component logs ACS Violation, not Completer Abort Error merely because it sent CA. Section 6.12.5 also specifies target-abort status and reporting. Continue AER handling in Chapter 12.

AER

Advanced Error Reporting

Base 6.0 §6.12.1.1, pp.753–754; §6.12.1.3, p.756; §6.12.2, p.757; §§6.12.5–6.12.6.2, pp.759–761.

Select a group before copying the Write to B and C

Multicast copies one Posted Request to configured outputs. Read Figure 6-14's windows, then §6.14.1's hit conditions, then membership. Only Memory Writes and Address Routed Messages can hit. A Non-Posted Memory Read inside the same address window remains unicast.

This separate simulated configuration gives all applicable Switch structures identical MC_Enable, MC_Num_Group, MC_Base_Address and MC_Index_Position. A/B/C have no Multicast Capability; B/C receive through Overlay. Both egress Ports support ECRC regeneration with the required AER and ECRC Check Capable support. Let M be the Multicast ID 0012h, Version 1 capability base:

ECRC

End-to-End Cyclic Redundancy Check

AER

Advanced Error Reporting

Use Figure 7-272 and Tables 7-244–7-246. MC_Max_Group=3 supports four groups; MC_Num_Group=3 configures four. Both use count-minus-one encoding. MC_Index_Position=12 gives 2¹²=4 KiB per window. The raw MC_Base_Address Register's low six bits encode Index Position; its trailing 0Ch is not part of the base address. With MC_Enable set, Index Position below 12 or Num_Group above Max_Group has undefined behavior. Base address bits below Index Position and those containing the group number must be zero.

MCG (Multicast Group) labels each window. Locate the address before selecting Ports.

A now sends a four-byte Memory Write to 80002500h with AT=10b, using a valid authorized translation. Section 6.14.1 gives MCG=((80002500h−80000000h)>>12)&3Fh=2 and offset 500h. The full hit range is 80000000h–80003FFFh; 80004000h is excluded.

MC_Enable, type and range must all match. After a Multicast Hit, Multicast processing replaces normal address routing. Only ACS Source Validation can still apply; P2P Request Redirect, Egress Control and Translation Blocking do not choose these copies' exits.

Base 6.0 §§6.14–6.14.1, Figure 6-14, pp.765–768; §§7.9.11–7.9.11.4, Figures 7-272–7-276, Tables 7-243–7-246, pp.1230–1234.

Distinguish blocked traffic, selected outputs and silent drops

At ingress DP1, MC_Block_All[2]=0 and MC_Block_Untranslated[2]=1 permit this AT=10b Multicast Write. Changing AT to 00b causes MC Blocked TLP, not ACS redirection. Compare independent packet conditions:

TLP

Transaction Layer Packet

After ingress checks, each Port's MC_Receive[2] selects an output. Bit 2 has mask 0000000000000004h. DP2 and DP3 receive copies; UP0 has no selected bit and gets no default upstream copy. DP1 cannot send back through the ingress, even with its own receive bit set.

If no eligible egress has MC_Receive[2] set, the packet is silently dropped. An MC_Block_All/MC_Block_Untranslated rejection instead drops the packet and logs/signals MC Blocked TLP under §6.14.4, with the blocking ingress responsible. Neither case creates an ordinary Posted Write Completion.

Existing Posted Ordering applies through replication and within each output stream. It does not promise simultaneous execution or all-or-nothing completion across recipients.

Base 6.0 §6.14.1, pp.766–768; §6.14.2, p.768; §6.14.4, p.769; §§7.9.11.5–7.9.11.7, Figures 7-277–7-279, Tables 7-247–7-249, pp.1234–1235.

Deliver copies to ordinary BARs without hiding ECRC errors

DP2/DP3 apply MC_Overlay, an egress address replacement. Figure 7-280/Table 7-250 decode raw 000000009000000Ch as base 90000000h and MC_Overlay_Size=12; DP3 uses base A0000000h. Size below 6 disables Overlay; zero does not specify a one-byte aperture.

Equation 6-1 preserves address bits 11:0 and replaces the rest from each egress Overlay base. Address 80002500h becomes 90000500h at DP2 and A0000500h at DP3, inside their preconfigured BARs. Overlay acts on exit, not on ingress, and does not allocate the Endpoint BARs.

ECRC (End-to-End CRC) covers TLP integrity and is affected by the modified address. Apply Table 6-12 separately to each outgoing copy:

The example's incoming ECRC passes, so each supported egress regenerates it over its modified TLP. If the original check fails, the egress sends an inverted regenerated ECRC, preserving a detectable error. Without regeneration support, it drops ECRC and clears TD. Output address, integrity handling and actual recipient data consumption remain successive observations.

Base 6.0 §6.14.5, Equation 6-1, Table 6-12, pp.769–770; §7.9.11.8, Figure 7-280/Table 7-250, p.1236; regeneration prerequisites: Table 7-244, p.1232.

Build the next reading route from the actual packet

Locate source, target, ingress, egress and direction before reading capability/control. For unicast P2P, connect source/translation checks, Direct Translated P2P and Table 6-11, then RC validation, Completions and errors. For Multicast, confirm the hit before ingress blocking, MC_Receive, output copies and Overlay. Missing destination data alone does not identify one failed component.

Before changing Multicast base or Index Position, §6.14.3 requires MC_Enable clear in every Function of the component for predictable results. Inconsistent common fields give indeterminate results. Even fields allowed to change at any time have ordered-update requirements. These static comparisons are not a live reconfiguration procedure. Linux P2P policy, IOMMU deployment and driver coordination need platform documents.

Base 6.0 §6.14.3, p.769; §7.9.11, p.1230.

Edition and complete source route

PCI Express Base Specification Revision 6.0 (6.0-1.0-PUB) supplies the rules. Printed and PDF-viewer page numbers match. All topology, register values and packet cases are author-created; no hardware was operated. No external website supplies PCIe technical claims.