PCIe Chapter 23: Power Budgeting, Allocation, and Emergency Reduction

Establish whose consumption is being reported

A Function is a software-visible unit; an add-in card can contain several Functions and Devices. Table 6-10 Power Budgeting Deployments (p.743) determines reporting scope from capability placement. For a multifunction Device with Power Budgeting in exactly one Function, the data covers the Device. When multiple Functions implement it, their data is per-Function and is summed according to the table.

Establish that scope before calculating watts. A multi-device card can report at card or Device level; adding every readable value without that distinction can count the same demand twice. Section 6.8.1 separately describes firmware allocations and the budget manager's responsibilities. The platform chooses its management process.

[Simulated data] The following data is created for teaching and does not represent specific hardware or a platform. Our card contains one single-function Endpoint. Function 0 covers all consumption, with no other Device or external power source. It draws from 12 V and 3.3 V rails and is currently in D0. Assume System Allocated=0, Extended Power Budgeting Supported=0 and exactly four non-extended data entries. Separately, the platform has already granted sufficient power under the applicable form factor and system budget.

Source: §6.8 Power Budgeting Mechanism, §6.8.1 System Power Budgeting Process Recommendations and Table 6-10, document/PDF pp.742–744.

Select data, decode conditions, then add matching rails

Walk the Extended Capability (configuration-space extension) list to ID 0004h, Version 1h; call its base C. Figure 7-136 locates 8-bit Data Select at C+04h, 32-bit Data at C+08h and Power Budgeting Capability at C+0Ch. Check System Allocated, then write a Data Select index and read Data. Indexing starts at zero, but its default is undefined, so explicitly select each entry.

Next use Figure 7-139 / Table 7-122. Base Power occupies bits [7:0]. Data Scale's low bits are [9:8], while its third bit is at bit 21. The scale bits are not contiguous. Our non-extended case has the third bit clear; encoding 001b gives 0.1×. Identify PM State, PM Sub State, Type and Power Rail before multiplying Base Power by the scale:

For entry 0, 000181B4h contains Base Power=B4h=180 and Data Scale=001b, giving 18 W. Type=011b means Sustained Power; Power Rail=000b means 12 V. Entry 1 matches the condition on the other rail, for 23 W D0 sustained consumption. Entries 2/3 use Type=111b, Maximum Power, and total 26 W.

Table 7-122 gives different measurement definitions: unless the form factor explicitly says otherwise, Sustained Power is a 5-second average at maximum throughput; Maximum Power uses a 1 ms moving window. The 23 W and 26 W describe different conditions and are not added together. A Thermal entry belongs to cooling assessment, not another electrical rail to add again.

Index 4 exceeds this case's four entries, so Data returns all zeros. On a device supporting Extended Power Budgeting, disabled extended entries are also hidden as zeros; interpret a zero with support, enable and index context. Table 7-122 also defines alternative power-range encodings when Base Power exceeds EFh under its stated conditions. F0h cannot always be treated as 240 W.

System Allocated=0 makes this case relevant to the responsible budget manager. If the bit is 1, the Device's budget is already included in the system budget; software must ignore its reported data for budgeting decisions to avoid counting it again. The Device still consumes power.

Source: §§7.8.1–7.8.1.5; Figure 7-136 (p.1090), Figure 7-137 / Table 7-120 (p.1091), Figure 7-139 / Table 7-122 (pp.1094–1097), Figure 7-140 / Table 7-123 (p.1098). Index and zero-return rules: pp.1091, 1093.

Does reporting 26 W grant the card 26 W?

Power Budgeting reports demand. Check the active grant mechanism separately. Under §6.9, Downstream Port Slot Capabilities supply the Slot Power Limit. Set_Slot_Power_Limit Message carries it to the Upstream Port across the same Link, where Device Capabilities exposes Captured Slot Power Limit Value/Scale. The limit applies to the entire adapter.

Before receiving a higher grant, the card must obey the applicable form-factor initial limit. The Slot mechanism does not permit an arbitrary lower value either. Section 6.8.3 separately defines Power Limit PM Sub State and Out of Band Power Limit mechanisms with distinct priority rules. Power Limit Enable and Power Limit PM Sub State may be configured through Configuration Writes only while all Device Functions are in D0uninitialized; changing them after any Function leaves that state has undefined behavior.

The runtime example therefore uses DPA. Power Budgeting has up to eight PM Sub States; DPA has up to 32 substates. Their numbers have no automatic correspondence. Function D0/D1 states and Link L1.1/L1.2 states describe still other mechanisms.

Source: §6.8.3 Power Limit Mechanismsm (title as printed) and §6.9 Slot Power Limit Control, document/PDF pp.744–746.

Reduce a D0 allocation from 26 W to 10 W

DPA is optional for applicable Endpoint Functions in D0. Substates run contiguously from 0 through Substate_Max. Substate 0 has the highest allocation; successive allocations must not increase. Software can select 2 directly from 0 without visiting 1. The Function must respond to Configuration Space accesses in every substate.

Assume our single-function card also implements DPA at base D. Figure 7-281 provides the layout; Figure 7-282 / Table 7-251 identifies ID 0016h, Version 1h. Build its allocation table in this order:

1. Figure 7-283 / Table 7-252: DPA Capability at D+04h reads 08031002h. Substate_Max=2 means three substates. Power Allocation Scale=01b gives 1.0×; Transition Latency Unit=00b gives 1 ms; Value 0=3 and Value 1=8.
2. Figure 7-284 / Table 7-253: DPA Latency Indicator at D+08h reads 00000004h. Bit 2=1 selects Value 1 for target substate 2; bits 0/1=0 select Value 0.
3. Figures 7-287 / 7-288 and Table 7-256: the Power Allocation Array starts at D+10h, with one byte per substate, not one DWORD.

The maximum transition latency into substate 2 is therefore 8 ms; returning to substate 0 uses 3 ms. The target substate selects the limit, and completion may occur sooner. DPA's scale encodings differ from Power Budgeting Data Scale; read their respective tables.

Source: §6.16 Dynamic Power Allocation (DPA) Capability, document/PDF pp.777–778; §7.9.12, Figures 7-281–7-288 and Tables 7-251–7-256, pp.1236–1241.

Read Control and Status together

Figure 7-285 / Table 7-254 places Status at D+0Ch: bits [4:0] are Substate Status and bit 8 is Substate Control Enabled. Initial Status=0100h means Enabled=1 and current substate 0. Figure 7-286 / Table 7-255 places Control at D+0Eh; bits [4:0] select the target. Its RsvdP bits (reserved bits whose values must be preserved) are initially zero here. Assume the Function remains in D0, with no Reset, emergency reduction or other software writes, and the reduction completes before the increase is requested.

During a reduction, Status must retain the higher allocation until completion. While Substate Control=2 but Substate Status still reports 0, reserve 26 W; do not give the difference to another card yet. Once Substate Status reports 2, the Function must obey its 10 W allocation.

During an increase, Substate Status must already indicate the higher allocation. Observing target 0 alone therefore does not establish completion. Prepare the 26 W budget before issuing the request, then use the target's maximum transition latency and any necessary Device information for subsequent actions. Status describes the allocation the Function must obey, not instantaneous sensed power or guaranteed application performance.

Section 6.16 permits a new target before the previous transition completes. The Device may alter an ongoing transition, or compare against the latest target after completion and transition again. Our case avoids intervening requests to show the two directions clearly. Preserve every Control write when interpreting a real trace; one final Status does not reconstruct that history.

Source: §6.16, document/PDF pp.777–778; §§7.9.12.4–7.9.12.5, Figures 7-285 / 7-286 and Tables 7-254 / 7-255, pp.1239–1240.

Does writing 1 enable Substate Control?

Check the attribute first. Substate Control Enabled is RW1C (write one to clear), in Status bit 8, not DPA Control. Hardware sets it after a Conventional Reset or FLR (Function Level Reset); software cannot directly set it back to 1.

For example, with Status=0102h in substate 2, writing 0100h to Status clears Enabled. Subsequent target writes to Control no longer directly initiate DPA transitions. This allows Device-specific software to take over allocation; its policy depends on that software and Device mechanism. Disabled does not promise a permanent 10 W allocation.

Source: §6.16, document/PDF p.777; §7.9.12.4 / Table 7-254, pp.1239–1240.

Will normal operation resume automatically after emergency reduction?

Emergency Power Reduction State is an optional fail-safe intended to prevent system damage and overrides the normal power mechanisms discussed here. Read Emergency Power Reduction Supported and Emergency Power Reduction Initialization Required in Device Capabilities 2, then use Table 6-16 to identify allowed triggers. Continue into §6.24's text for exit behavior.

For example, Supported=10b permits the applicable form-factor mechanism only if that form factor actually defines such a request. Vendor-specific and autonomous triggers also follow Table 6-16. There is no universal standard Configuration-bit write sequence that triggers every platform.

Initialization Required=1 can also leave the port in DL_Up, so accessible Configuration Space alone does not establish that software reinitialization is unnecessary. Notification of required reinitialization and external signaling details require platform, form-factor or vendor documentation. Power Budgeting must also report the appropriate emergency-state consumption; the normal D0 26 W value cannot simply be reused.

Source: §6.24 Emergency Power Reduction State, Table 6-16 Emergency Power Reduction Supported Values, document/PDF pp.812–813; §7.5.3.15, p.993; §7.8.1.4, p.1097.

Which PF/VF power belongs in the same allocation?

PF

Physical Function

VF

Virtual Function

A PF (Physical Function) and VF (Virtual Function) have distinct roles in SR-IOV (Single Root I/O Virtualization). A PF may implement Power Budgeting, covering all associated VFs; VFs must not implement it. VF DPA allocation is likewise managed through its associated PF; VFs must not implement DPA Capability.

Some or all Functions of a general multifunction Device may implement DPA; their allocations are summed. One Function's DPA may also account for Functions lacking it, with implementation-specific associations. Do not copy the single-function case into an extra 26 W allocation for every VF.

D-states follow §5.10 separately. PFs must implement Power Management Capability; VFs may implement it. A VF without it behaves as if programmed into its PF's equivalent power state. When a VF implements it, putting the PF in a lower-power state than the VF has undefined behavior; software should lower the VFs first. That differs from changing DPA allocation while remaining in D0.

Source: §§5.10–5.10.1, document/PDF p.655; §6.16.1, p.778; §7.8.1, p.1090.

Edition and sources

This chapter uses PCI Express Base Specification Revision 6.0 (6.0-1.0-PUB). Document and PDF page numbers match. Example values and observations are author assumptions; no hardware measurement was performed.