PCIe Chapter 19: LTSSM, Equalization, and Retimers

Find the state, then its transition rules

For an LTSSM (Link Training and Status State Machine) log, establish the Port, Link, direction, and time first. Figure 4-48 locates the main state; §4.2.6 explains its task; §4.2.7 supplies substate actions, receive conditions, and timeouts. Read them together.

This chapter works through Polling during initial Link establishment. Use Figure 4-49 for entry after Receiver Detection (far-end termination detection), then Figure 4-50 for Polling.Active and Polling.Configuration. Later sections connect speed changes, equalization, and Retimers to the observations needed for each situation.

Base 6.0 §4.2.6 Link Training and Status State Machine (LTSSM) Descriptions (pp.444–452); §4.2.7 Link Training and Status State Rules; Figure 4-48 Main State Diagram for Link Training and Status State Machine (pp.452–454); Figures 4-49 Detect Substate Machine (p.456) and 4-50 Polling Substate Machine (p.464).

What remains after seeing a valid TS1 or TS2?

One valid sequence is one successful reception. Transition rules also depend on consecutive reception, transmission counts, and the Lane set. TS1 and TS2 are Training Sequence Ordered Sets. Each end transmits its own sequences and independently checks received content.

Base 6.0 §4.2.7.1.2 Detect.Active (p.456); §4.2.7.2.1 Polling.Active (pp.457–458); §§4.2.7.2.3 Polling.Configuration and 4.2.7.2.4 Polling.Speed (p.463); Figure 4-50 (p.464); §4.2.7.3 Configuration (p.464 onward).

A timeout does not always mean a return to Detect

The preceding case takes normal transitions. A stalled Link requires the timeout rules for the specific substate.

Section 4.2.6 gives LTSSM timeouts a −0 / +50% tolerance unless stated otherwise. Nominal 24 ms and 48 ms therefore have upper limits of 36 ms and 72 ms. Do not require every implementation to transition at exactly 24.000 ms or 48.000 ms. Establish the timer origin, observation time, and continuity of the record.

The Polling.Active timeout path uses “any Lane” and an implementation-specific predetermined Lane set, unlike the normal all-detected-Lanes condition. It permits further training without identifying a broken Lane. Polling.Compliance can also follow Enter Compliance or specified training-control conditions; recover the actual control and received sequence history.

Base 6.0 §4.2.6 (p.444); §4.2.7.1.2 (p.456); §4.2.7.2.1 (pp.457–458); §4.2.7.2.3 (p.463).

Why can Link Training be zero during Polling?

Link Training in Link Status describes selected conditions, not every LTSSM state. This case reads the Root Port. The bit is inapplicable and hardwired to zero in Endpoints, Switch Upstream Ports, and PCI Express to PCI/PCI-X Bridges.

Use Table 4-48 for state mapping, then Table 7-26 for field applicability. The former's LinkUp is a Physical Layer indication to the Data Link Layer. Data Link Layer Link Active in Link Status instead reports DL_Active when reporting is supported. See Chapter 8 and Chapter 17 for the complete cross-layer explanation.

Base 6.0 Table 4-48 Link Status Mapped to the LTSSM (p.453); §7.5.3.8, Figure 7-29, and Table 7-26 Link Status Register (pp.978–979).

Follow Recovery when increasing speed

Initial training reaches L0 at 2.5 GT/s even when both ends support higher rates. A later speed change uses Recovery from L0. Advertised higher rates during Polling are not the current signaling rate. Section 4.2.7.2.4 explicitly makes Polling.Speed unreachable.

Equalization (per-Lane transmitter/receiver adjustment to compensate for the channel) has rate-specific procedures. Section 4.2.4 requires the applicable procedure for the first transition to each rate at or above 8.0 GT/s, while defining jointly supported/advertised bypass mechanisms. Separate the normal procedure, bypass to the highest NRZ rate, and No Equalization Needed. One end's bit does not justify skipping work across the whole path.

NRZ

Non-Return-to-Zero

Connect the requesting end, Recovery substates, applicable equalization, and final speed/width. The two-ended Register and state walkthrough in Chapter 8 supplies the lookup entry. Recovery alone does not imply re-enumeration or clearing every Data Link state; actual LinkUp and Reset history matter.

Base 6.0 §4.2.6.4 (p.445); §4.2.7.2.4 and the p.464 note Support for Higher Data Rates Than 2.5 GT/s; §4.2.4 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates (pp.392–393).

Separate one Link from its electrical segments

A Retimer understands Physical Layer protocol and restores signal timing. Figure 4-61 marks the full Link and its Link Segments. Each Retimer has two Pseudo Ports whose orientation is determined dynamically during Configuration.

Next read the modes in §4.3.2. Forwarding mode forwards applicable Symbols and Electrical Idle. Execution mode participates in specified cases such as Polling.Compliance and equalization Phases 2/3. Locate the Pseudo Port and direction when investigating one segment rather than assigning the Root Port's overall result to every segment.

Base 6.0 permits at most two Retimers per Link, with possible additional form-factor limits. Transparency to Data Link and Transaction Layers means no extra Bridge bus-number assignment and no independent TLP Ack/Replay domain per electrical segment. Electrical compliance still needs applicable Chapter 8 requirements and measurements.

TLP

Transaction Layer Packet

Base 6.0 §4.3 Retimers (pp.564–565); §4.3.2 and Figure 4-61 Supported Retimer Topologies (pp.566–567). The table is an author-organized topology illustration.

Check power and test branches by their purpose

L0p (partial-Lane power saving within L0) is Flit-only, targets a symmetric width, and keeps at least one active Lane per direction. It does not first leave L0 to rebuild the entire Link; the two ends can briefly use different widths during a transition. L0s is a separate fast power state and must not be supported/advertised in Flit Mode, on Retimer Links, or with separate reference clocks and independent SSC (Spread Spectrum Clocking).

Polling.Compliance serves testing; the Loopback Lead requests the test and the Follower returns data; Hot Reset uses in-band signaling to reset a configured Link and associated downstream device. Figure 4-48 has distinct branches for them. A trace with “no TLP” still needs the state and entry conditions to distinguish training, power saving, and testing. See Chapter 9 for L1, Function power states, and platform policy.

TLP

Transaction Layer Packet

Base 6.0 §4.2.6.2 (p.444); §§4.2.6.6–4.2.6.7 (pp.445–447); Figure 4-47 transition explanation (p.450); §§4.2.6.8–4.2.6.12 (pp.451–452).

Does x8 becoming x4 mean a width-training failure?

Teaching assumptions: One Link connects Switch Downstream Port A to Endpoint Upstream Port B. Its configured width is x8 and it operates in Flit Mode. Both report Receiver L0p Supported and Remote L0p Supported, both have L0p Enable set, and A has Hardware Autonomous Width Disable clear. These are illustrative conditions.

Figure 7-120 locates Device 3 Extended Capability registers. Receiver L0p Supported describes the local receiver; Remote L0p Supported describes the partner; L0p Enable controls requests and Ack responses. Support and permission do not establish the current active width.

In Table 7-109, writing Target Link Width 010b at A with L0p enabled initiates a directed x4 request. The field is a request; the later exchange and Lane state establish its result.

After Ack, each Port independently sends EIOSQ on lanes to be deactivated at the next scheduled SKP interval, then enters Electrical Idle on those lanes; active lanes continue transmitting Flits. Nak, timeouts, asynchronous lane behavior, and Recovery follow the applicable §4.2.6.7 branches.

L0p cannot reactivate lanes disabled during Configuration. On entering Recovery, the Link returns to the width configured at the last entry to L0. Determine whether an x4 observation reflects temporary L0p operation or a configuration/training result. Base 6.0 §4.2.6.7, §5.4.1.2 and §7.7.9.2–§7.7.9.4, pp.445–447, 626, and 1073–1077.

Why do the register and packet encode x4 differently?

Use Figure 3-15 to identify a Link Management DLLP, then Table 4-44 to interpret the fields. These author-created four-byte DLLP Payloads occupy Flit DLP 2–5; they are not complete Flits and omit DLP 0–1 and Flit CRC.

DLLP

Data Link Layer Packet

On a phone, scroll the table sideways to see all columns.

Device Control 3 uses 010b for target x4; the DLLP width field uses 0100b. Receivers silently ignore the reserved Type, Cmd, or applicable field encodings listed in Table 4-44.

The case assumes a valid Flit and DLP 0 Type of DLLP Payload=0, selecting a DLLP Payload in DLP 2–5. CRC, FEC, and the rest of the Flit are outside these four bytes. Base 6.0 Figure 3-15, Table 4-44, Figure 4-30 and Table 4-16, pp.285, 359–360, and 448–449.

FEC

Forward Error Correction

How are the two ends' exit latency values combined?

Teaching assumptions: Port A reports Port L0p Exit Latency 010b (2 to less than 4 µs) and associated Retimer L0p Exit Latency 001b (1 to less than 2 µs). Data Link Feature Status has Remote Data Link Feature Supported Valid=1 and Remote L0p Exit Latency 011b (4 to less than 8 µs).

Table 7-108 forms Local L0p Exit Latency as the larger of Port and associated Retimer, yielding 010b. Tables 7-64 and 7-65 describe the Data Link Feature exchange; once the remote information is valid, the effective Link latency is the larger of Local and Remote, in this case the 011b range.

The encodings are specified latency ranges, not measurements of this exchange. If Remote Valid=0, obtain valid exchange information; a default zero is not proof that the partner is below 1 µs. Base 6.0 Tables 7-64, 7-65, and 7-108, pp.1035–1037 and 1074.

Edition and sources

PCI Express Base Specification Revision 6.0 (6.0-1.0-PUB) is the authority. Printed and PDF-viewer page numbers match at these locations. Topology and counts are author-created; capture-channel labels are not assigned Lane Numbers.