PCIe Chapter 10: Device and Link Power Management

Separate function and link power before configuration

Function D-states and link L-states describe different objects. A function in D0 can use a link that enters power saving through ASPM (Active State Power Management) when the required conditions hold.

Specification route: Tables 5-1/5-2 → PM and link fields → L1 PM Substates in Figures 7-146–7-150 → latency tolerance and exit timing.

Function D-states and Link L-states are separate

D0 is the normal Function state, but ASPM can save Link power during idle periods in D0. D1/D2 are optional. D3hot retains main power; D3cold lacks main power but may retain auxiliary power for wake. D0uninitialized after reset does not establish readiness of the work interface.

L0 supports transmission. L0s can operate independently by direction, but is unsupported in Flit Mode, with Retimers, or under specified independent-SSC clock conditions. L0p is Flit-only and idles some Lanes while retaining at least one active Lane in each direction. L1 can have L1.0/L1.1/L1.2 substates. L2/L3 follow main-power removal and differ by the presence of Vaux.

Read PM capabilities, then construct the D0 write correctly

Conventional Capability ID=0x01 identifies PM. An authored full-DWORD read at 0x40 returns 0xC8035001: ID=0x01, Next=0x50, Version=3, no D1/D2 support. PME_Support=(value >> 27) & 0x1F = 0x19 allows PME from D0, D3hot, and D3cold. Assume no optional Data Register, Aux_Current=0 using self-power, and necessary power availability. This is capability evidence, not proof of a complete wake path.

PME

Power Management Event

Assume no concurrent changes or new events. No_Soft_Reset=1 preserves internal state for the specified software D3hot-to-D0 transition, returning to D0active; it does not remove recovery delays. Immediate Readiness=0 and no other timing exception require at least 10 ms before further access, including Configuration. No_Soft_Reset=0 requires full reinitialization and does not guarantee old state was cleared. D3cold, Fundamental Reset, and DL_Down from L2/L3 Ready do not inherit this preservation guarantee.

PowerState has no D3cold encoding. Unsupported D1/D2 writes complete normally without changing state. PME_Status can record a qualifying event even with PME_En=0. Entering D3hot still requires handling outstanding transactions and state preservation.

ASPM enablement needs capabilities and a latency policy

ASPM manages an idle Link in D0; PCI-PM uses software-directed D-state changes. An ordinary non-ARI multifunction device must have all Functions outside D0 before initiating L1 on behalf of PCI-PM.

Inspect both Link Capabilities ASPM Support fields, then Link Control ASPM Control. Enablement does not report current L1 residency. Compare Link Capabilities L1 Exit Latency with Endpoint Device Capabilities L1 Acceptable Latency across the path. Exits can overlap across Links, so adding every Port's latency is incorrect; Figure 5-8's example finishes at T+34 μs.

Follow L1 entry, then reconnect it to transaction traffic

Use Figure 7-27/Table 7-23 to check ASPM Support, then Figure 7-28/Table 7-24 for ASPM Control. Those settings permit L1 entry; Figure 5-7 explains the actual exchange and the actions at each end.

In the original Figure 5-7, T/D/P denote Transaction, Data Link, and Physical Layers. Follow time downward to see when each end blocks new packet scheduling and how the two directions enter Electrical Idle in sequence. Interpret these activity indicators separately from the Data Link state names in Figure 3-2.

Waiting for Link-level acknowledgement of the last TLP drains the Retry Buffer (saved retransmission copies). PM_Request_Ack is a Data Link Layer Packet (DLLP) accepting L1 entry. It serves a different purpose from an Ack DLLP acknowledging TLPs or a Completion returning an end-to-end read result. An earlier Memory Read may still be awaiting its Completion and must remain tracked; entering L1 does not complete that Transaction.

Continue the accepted-entry case: if a Memory Write becomes ready for this Link after the Switch sends PM_Request_Ack, the Switch must finish entering L1 and then initiate exit, even without enough Flow Control credits to transmit that packet. Once back in L0, normal credit and scheduling rules apply. Then read Figure 4-54: L1.Entry proceeds to L1.Idle, which exits to Recovery when the applicable conditions hold, followed by the applicable path back to L0. This is the normal L1 exit path.

Completion Timeout keeps counting in L1, while Flow Control Update timers are frozen. On the rejection path in Figure 5-6, PM_Active_State_Nak is a Message TLP, distinct from a Nak DLLP requesting replay; that figure assumes L0s is enabled. A trace interval without TLPs still needs PM negotiation, Electrical Idle, and LTSSM history to validate an analyzer's L1 label.

LTSSM

Link Training and Status State Machine

Configure L1.2 using both ends and the required order

Separate list traversal happens to locate ID=0x001E, Version=1, Next=0 at 0x200 on both ends. Version 1 lacks the +0x10 Status Register. Both low-five capability fields are 0x1F, indicating all four Substate capabilities and overall support. Advertised T_POWER_ON is 10/100 μs, and common-mode restoration is 10/20 μs. Configured Control 2 Value=10, Scale=1 gives 100 μs. Control 1 enables only ASPM L1.2 at bit 2. Common_Mode_Restore_Time is set to 20 μs on the Downstream Port and is RsvdP on the Upstream Port.

The platform has validated these settings for the connection; taking the larger advertised values is not asserted as a universal algorithm. Both ends must support the selected Substate. Configure ASPM Substates while ASPM L1 is disabled, and PCI-PM Substates while in D0. Program applicable timing and identical LTR thresholds first, then enable corresponding bits on the Downstream Port before the Upstream Port. Disable in the reverse order. Clear applicable L1.2 Enables before changing timing fields; restore ASPM L1 under policy afterward.

LTR

Latency Tolerance Reporting

The same Enable can produce different entry decisions

Control 1 threshold Value=128, Scale=2 gives 128 × 1024 ns=131072 ns (131.072 μs). Assume ASPM L1.0, deasserted CLKREQ#, and all other entry conditions satisfied. Latest valid snoop/no-snoop LTR requirements of 204800/102400 ns fail because no-snoop is below threshold. Changing them to 204800/153600 ns satisfies both, requiring entry under these assumptions.

No requirement for a traffic class is a separate branch, not Requirement=1 with Value=0; the latter requests the best possible service. These are latest valid reports, not Max Latency Register limits. LTR is also not a hard Root Complex latency guarantee. L1.1 is not enabled here, so it is not an assumed fallback. Before enabling Endpoint LTR, the Root Complex and intervening Switches must support it, with devices closest to the Root Port enabled first.

Wake restores communication before identifying the source

L2 cannot carry ordinary TLPs. The device uses form-factor-appropriate WAKE# or Beacon to request power, clock, and Link restoration, then sends PM_PME with its Requester ID. PME_En, auxiliary power, and platform routing must cooperate. (§5.3.3.1–§5.3.3.2, pp.615–616.)

Platform background: ACPI 6.6 §7.3.8–§7.3.11 describes D0/D3hot power dependencies through _PR0/_PR3, not PCIe Registers. Document pp.497–498 correspond to PDF pp.568–569.

Check whether the conditions are sufficient