NVMe Base 2.4 Chapter 4: SQE, CQE, Status, PRP, and SGL
00.01.An NVMe command must identify the operation, target namespace, and data location. Its completion must identify the command and report the outcome. This note uses these two directions to explain SQEs, CQEs, and PRP/SGL data pointers.
- namespace
- Namespace, a formatted quantity of non-volatile memory accessed by a host through a controller.
- NVMe
- Non-Volatile Memory Express, the specification family for a host interface to a non-volatile-memory subsystem.
- PRP
- Physical Region Page, a pointer format describing a host-addressable data buffer in memory-page units.
- SGL
- Scatter Gather List, a descriptor-and-segment format for one or more data-buffer regions.
The main ideas
Command contents: SQE
01-01Understand command identifiers, opcodes, and data pointers.
Completion results: CQE
02-01Distinguish new entries, command identity, and status codes.
Data addresses: PRP/SGL
03-01Connect memory-page concepts to NVMe data transfers.
Other shared structures
04-01Understand representations for Feature values, identifiers, lists, and text.
00.02.Command and completion entries are records in queues; data pointers identify the data involved in a transfer. Distinguishing the command record from its transfer data is the starting point for the field layouts.
Connecting the main ideas
00.03.Separate an operation into the request in the SQE, data locations described by PRP/SGL, and the command identity and result in the CQE. Identifiers and lists help select the intended objects.
- CQE
- Completion Queue Entry, one completion-result structure in a CQ.
- SQE
- Submission Queue Entry, one command structure in an SQ.
00.04.The lessons move from common layouts to bits, lengths, and pointers. The aim is to calculate transfer size, interpret pointers correctly, and associate a completion with its command. Establish units before calculations rather than inferring them from field names.
01 The common SQE format and command fields
01.01.The common SQE fixes the locations of CDW0, NSID, metadata/data pointers, and CDW10-15. OPC selects the command, CID creates the completion association, and PSDT selects DPTR interpretation. Only after these common fields are established should command-specific CDW10-15 definitions be applied. Figures 92-94 are the coordinate system for all later command construction.
- metadata
- Additional information stored with a logical block; it can contain protection information or serve other purposes.
- DPTR
- Data Pointer, the SQE field identifying a command data buffer.
- NSID
- Namespace Identifier, a controller-visible numeric handle for a namespace; the identifier is not the namespace object itself.
- PSDT
- PRP or SGL for Data Transfer, the CDW0 field selecting PRP or SGL interpretation for DPTR.
- CDW
- CDW (Command Dword): a 32-bit command field. In CDW10, 10 is the field index, not a byte offset.
- CID
- Command Identifier, used with the SQ identifier to identify an outstanding command.
01.02.The common Admin and I/O SQE is 64 bytes. CDW0, NSID, data pointers, and CDW10-15 establish the common layout before each command defines command-specific content.
- Admin
- Administrative, the control path used to create, configure, query, or manage controllers and queues.
- I/O
- Input/Output, the class of data operations performed on a namespace.
Sources: Base 2.4 §4.1.1
Source: NVME-BASE-2.4, Rev. 2.4, §4.1.1, printed pages 139-143, PDF pages 165-169
| SQE region | Information provided by the host | Selecting the right field definition |
|---|---|---|
| CDW0 | Command identity and data-pointer selector | Common to all commands |
| NSID | Namespace scope | When unused, clear or use a special value only as the command defines |
| MPTR/DPTR | Metadata and data buffers | Selected by PSDT and command rules |
| CDW10-15 | Command-specific payload | Never borrow semantics from another command |
- MPTR
- Metadata Pointer, the SQE field identifying a separate metadata buffer.
02 CQEs: new entries, command identity, and results
02.01.The host first uses the Phase Tag to determine whether a CQ slot contains a new completion. After ownership is established, SQID/CID recovers the command; SCT then selects the status category before SC, DNR, and CRD are interpreted. Figures 97-109 must be read in this order so a stale CQE or wrong category is not mistaken for a command failure.
- Host
- The system running the operating system and issuing NVMe commands.
- CRD
- Command Retry Delay, the status field selecting a controller-recommended retry delay.
- DNR
- Do Not Retry, a CQE-status bit indicating that retrying the same command is not expected to succeed.
- SCT
- Status Code Type: selects the completion-status category and is interpreted with SC.
- CQ
- Completion Queue, the queue into which a controller posts command completions.
- SC
- Status Code: identifies the completion result within the selected SCT category.
02.02.The common CQE is at least 16 bytes. If multiple writes construct it, the Phase Tag shall be updated in the last write so the host does not consume a partial entry.
Sources: Base 2.4 §4.2.1
Source: NVME-BASE-2.4, Rev. 2.4, §4.2.1, printed pages 144-145, PDF pages 170-171
| Completion-status field | Question answered | Other required information |
|---|---|---|
| SCT | Status category | Interpret SCT before looking up SC |
| SC | Specific result within the category | Never interpret without SCT |
| DNR | Expectation for retrying the same command | Not synonymous with permanent hardware failure |
| CRD | Recommended retry-delay selector | Use only for an applicable status |
03 How PRPs describe data across pages
03.01.PRP1 may address any byte within the first memory page, so first-segment capacity is page_size minus offset. If data crosses that page, PRP2 represents either the second page or a PRP List depending on remaining length; later page addresses must be page aligned. Figures 110-113 define address calculation, not merely pointer names.
- offset
- offset: a displacement measured from a stated start. It answers “how far from the start,” unlike an index.
03.02.A fixed-size PRP entry points to a physical memory page. The first entry may contain a page offset; subsequent PRPs shall obey page alignment, and transfer length determines the required entry count.
- page offset
- page offset: the starting displacement inside the first memory page; after a page boundary, the next page pointer determines the location.
Sources: Base 2.4 §4.3.1
Source: NVME-BASE-2.4, Rev. 2.4, §4.3.1, printed pages 158-159, PDF pages 184-185
| Page-span case | Meaning of PRP2 | Pointer and alignment requirement |
|---|---|---|
| Data stays in first page | PRP1 is sufficient | PRP2 does not carry another segment |
| Remaining data fits one page | PRP2 addresses the second data page | Address is page aligned |
| Remaining data exceeds one page | PRP2 addresses a PRP List | List entries address data pages |
04 SGL data and segment descriptors
04.01.An SGL descriptor combines type/subtype, address, and length. A Data Block addresses data, Segment and Last Segment address more descriptors, and Bit Bucket represents data that need not be stored in memory. Figures 114-125 require type-first decoding; blindly following an address before decoding type is incorrect.
04.02.An SGL describes a data buffer through one or more descriptors and segments. SGL length shall equal or exceed the requested transfer length; this report covers only generic descriptors applicable to PCIe.
- PCIe
- PCI Express, the transport and device interconnect used by an NVMe memory-based controller.
Sources: Base 2.4 §4.3.2
Source: NVME-BASE-2.4, Rev. 2.4, §4.3.2, printed pages 159-166, PDF pages 185-192
| Pointer or descriptor type | Meaning of address and length | Object reached by following the pointer |
|---|---|---|
| PRP | Page-based addresses | First-page offset plus later-page alignment |
| SGL Data Block | Address plus byte length | A descriptor represents a data region |
| SGL Segment | Address plus descriptor-list length | Points to more descriptors, not data |
| Bit Bucket | Consumes transfer length only | Does not represent a readable or writable memory buffer |
05 Feature values, identifiers, lists, and strings
05.01.Establish what a value represents before interpreting it: Feature values distinguish active from saved state, identifiers have an identity scope, and lists and strings each have layout and length rules.
05.02.A Feature may have default, saved, and current values. Saved-value support and persistence across resets or power cycles are determined from SSFS and each Feature capability.
Sources: Base 2.4 §4.4
Source: NVME-BASE-2.4, Rev. 2.4, §4.4, printed pages 166-169, PDF pages 192-195
| Identifier or list | Object and format identified | Length and count interpretation |
|---|---|---|
| VID/SSVID | Vendor and subsystem vendor identifiers | Interpret each field for its own object |
| SN/MN | Product serial and model strings | Read fixed lengths and padding rules |
| EUI64/NGUID/UUID | Different object identifier formats | Widths and identity scopes are not interchangeable |
| Controller List | NUMCIDS followed by 16-bit IDs | Has an explicit count header |
| Namespace List | Direct sequence of 32-bit NSIDs | Does not have the Controller List count header |
- NUMCIDS
- Number of Controller Identifiers: the count of valid controller IDs in a Controller List.
- EUI64
- 64-bit Extended Unique Identifier, a 64-bit identifier constructed from IEEE-assigned space.
- NGUID
- Namespace Globally Unique Identifier, a 128-bit global identifier for a namespace.
- SSVID
- Subsystem Vendor ID, the PCI identifier for a subsystem vendor.
- UUID
- Universally Unique Identifier, a 128-bit identifier whose association scope is defined by the containing structure.
- VID
- Vendor ID, a PCI-SIG-assigned identifier for a vendor.
- MN
- Model Number, a string identifying a product model.
- SN
- Serial Number, a string identifying a product instance.
Where to continue in the specification
06.01.Use the flow above to frame the problem, then open the corresponding sections for fields and full conditions. The Chinese tutorial also explains every in-scope figure with its takeaway, example, and details.
| Concept to explain | Specification sections |
|---|---|
| The common SQE format and command fields | Base 2.4 §4.1.1 |
| CQEs: new entries, command identity, and results | Base 2.4 §4.2.1 · Base 2.4 §4.2.3 · Base 2.4 §4.2.4 |
| How PRPs describe data across pages | Base 2.4 §4.3.1 · Base 2.4 §4.1.1 |
| SGL data and segment descriptors | Base 2.4 §4.3.2 · Base 2.4 §4.1.1 |
| Feature values, identifiers, lists, and strings | Base 2.4 §4.4 · Base 2.4 §4.5 · Base 2.4 §4.6 · Base 2.4 §4.8 |
Check your understanding
1. If two SQs use CID=5, how is a completion associated with its command?
07.01.CID is unique among outstanding commands within one SQ. Interpret it together with the SQ identifier in the completion information to find the command in the correct queue.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §4.1.1, printed pages 140, PDF pages 166
Source: NVME-BASE-2.4, Rev. 2.4, §4.2.1, printed pages 144-145, PDF pages 170-171
2. Does a CQE with the expected Phase Tag establish command success?
07.02.The Phase Tag identifies a new completion at that location. Success is determined from status information such as Status Code Type and Status Code. Freshness and success are separate decisions.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §4.2.4, printed pages 155-158, PDF pages 181-184
Source: NVME-BASE-2.4, Rev. 2.4, §4.2.3, printed pages 145-155, PDF pages 171-181
3. Why can a PRP1 starting inside a page not imply physically contiguous memory across the next page?
07.03.PRP1 supplies the page offset of the first segment. Subsequent PRP page addresses or a PRP List find data after a boundary. A logically continuous host buffer need not occupy physically adjacent pages.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §4.3.1, printed pages 158-159, PDF pages 184-185
4. Why inspect PSDT before interpreting DPTR?
07.04.The same DPTR bits can represent PRPs or an SGL depending on the selected format. PSDT and command support determine whether to interpret them as page pointers or segment descriptors.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §4.1.1, printed pages 140-142, PDF pages 166-168
Source: NVME-BASE-2.4, Rev. 2.4, §4.3.2, printed pages 159-166, PDF pages 185-192


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