繁體中文 00.01.Before a controller can process I/O, its interface, queues, and operating state must be established. This note follows the controller lifecycle through capabilities, initialization, command processing, memory resources, shutdown, resets, and firmware activation.controllerController, the entity that implements the NVMe interface, fetches commands, and reports completions.I/OInput/Output, the class of data operations performed on a namespace. The main ideas 01Startup and capabilities01-01Identify the controller, configure required properties, and establish readiness. 02Queues and processing02-01Understand queue positions, doorbell updates, and arbitration. 03Resources and lifecycle03-01Distinguish capacity, controller memory, and the scope of state changes. 00.02.Submission queues hold commands from the host, and completion queues...
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NVMe Base 2.4 Chapter 3: Controllers, Queues, Initialization, and Resets
00.01.Before a controller can process I/O, its interface, queues, and operating state must be established. This note follows the controller lifecycle through capabilities, initialization, command processing, memory resources, shutdown, resets, and firmware activation.
- controller
- Controller, the entity that implements the NVMe interface, fetches commands, and reports completions.
- I/O
- Input/Output, the class of data operations performed on a namespace.
The main ideas
Startup and capabilities
01-01Identify the controller, configure required properties, and establish readiness.
Queues and processing
02-01Understand queue positions, doorbell updates, and arbitration.
Resources and lifecycle
03-01Distinguish capacity, controller memory, and the scope of state changes.
00.02.Submission queues hold commands from the host, and completion queues hold results from the controller. The host establishes these shared mechanisms before using commands such as reads and writes.
- Host
- The system running the operating system and issuing NVMe commands.
Connecting the main ideas
00.03.A controller becomes usable through capability reporting, memory and queue configuration, enablement, and readiness confirmation. During operation it selects work, manages namespaces and controller memory, and eventually handles shutdown or reset.
00.04.This lifecycle connects properties that report capabilities, accept host choices, or report current state. The aim is to identify who acts at each stage, which information permits progress, and what must be re-established after shutdown or reset.
01 Controller types, identifiers, and capabilities
01.01.Controller type answers what work a controller can perform, Controller ID answers which controller it is, and support-requirement Figures answer the required support level of a command, log, or feature in a particular context. Figures 23-32 belong in one reading sequence, but the three questions cannot be collapsed into one Boolean.
01.02.A memory-based controller shall support only the static controller model.
Sources: Base 2.4 §3.1.1
Source: NVME-BASE-2.4, Rev. 2.4, §3.1.1, printed pages 38, PDF pages 64
| Controller type or marker | Work it can perform | How support is established |
|---|---|---|
| I/O controller | Can execute user-data I/O | Optional capabilities still require individual checks |
| Administrative controller | Management purpose without data I/O commands | An Admin Queue does not make it an I/O controller |
| Support marker | Expresses support strength for a row and context | Read each support marker together with its column and footnote |
- Administrative controller
- Administrative controller, a management-oriented controller type that does not execute user-data I/O commands.
- I/O controller
- I/O controller, a controller type capable of executing user-data I/O commands.
- Admin
- Administrative, the control path used to create, configure, query, or manage controllers and queues.
02 Initialization from configuration to CSTS.RDY
02.01.Properties are not an independent register list. CAP constrains page-size, queue, and timeout capabilities; AQA, ASQ, and ACQ establish Admin queues; CC selects settings and enables the controller; CSTS.RDY finally declares readiness for normal command processing. Figures 33-46 and Figure 57 should be read along this causal chain.
- CSTS
- Controller Status, the property through which a controller reports ready, fatal-status, and shutdown state.
- ACQ
- Admin Completion Queue Base Address, the base address of the Admin CQ in addressable memory.
- AQA
- Admin Queue Attributes, the property describing Admin SQ and Admin CQ sizes.
- ASQ
- Admin Submission Queue Base Address, the base address of the Admin SQ in addressable memory.
- CAP
- Controller Capabilities, the controller property at offset 00h that reports queue, page-size, timeout, and other capabilities.
- RDY
- Ready, the CSTS bit indicating whether the controller is ready for normal command processing.
- CC
- Controller Configuration, the property through which the host selects settings and enables or disables a controller.
02.02.The host shall access a property at its starting offset using the specified width; the PCIe Transport adds the access rules for a memory-based controller.
- offset
- offset: a displacement measured from a stated start. It answers “how far from the start,” unlike an index.
- PCIe
- PCI Express, the transport and device interconnect used by an NVMe memory-based controller.
Sources: Base 2.4 §3.1.4
Source: NVME-BASE-2.4, Rev. 2.4, §3.1.4, printed pages 52-54, PDF pages 78-80
| Property or setting | Host/controller contribution | Order during initialization |
|---|---|---|
| CAP | Capabilities and limits | Read before writing configuration |
| AQA/ASQ/ACQ | Admin-queue sizes and addresses | Must match page and alignment capabilities |
| CC | Host selections and enable | Written values must be compatible with CAP |
| CSTS | Controller-reported state | RDY, CFS, and SHST are not interchangeable |
- SHST
- Shutdown Status, the CSTS field through which the controller reports shutdown progress.
03 Queue positions and command selection
03.01.Figures 73 and 74 define empty/full state for a queue, while Figures 80 and 81 define arbitration among SQs competing for controller service. The first problem concerns head/tail state within one ring; the second selects among candidate SQs. Priority belongs to the SQ, not to each command as an independent priority.
03.02.A PCIe queue is a circular buffer in host-addressable memory with head and tail pointers. The host creates an I/O Completion Queue before its Submission Queue and advances pointers through doorbells.
Sources: Base 2.4 §3.3.1
Source: NVME-BASE-2.4, Rev. 2.4, §3.3.1, printed pages 88-91, PDF pages 114-117
| Queue state or arbitration | Decision governed | What it does not determine |
|---|---|---|
| Empty | Head equals tail under the empty ownership definition | No entry can be fetched |
| Full | The next tail would reach an unreleased head | The host must not overwrite an entry |
| Round Robin | Candidate SQs take turns receiving service | Completion order is not submission order |
| Weighted RR + Urgent | Priority class and weight influence selection | Interpret only under the applicable configuration |
04 Namespaces, CMB, PMR, and capacity
04.01.CMB and PMR properties describe the location, capability, and state of controller-exposed memory regions; capacity Figures 86-89 describe available or allocated capacity at NVM-subsystem levels. Both concern memory, but they are different spaces and cannot be merged into one free-capacity value.
- CMB
- Controller Memory Buffer, controller-provided memory in which selected queues or data structures may reside.
- NVM
- Non-Volatile Memory, memory that retains data without power.
- PMR
- Persistent Memory Region, a controller-exposed memory region with persistence semantics.
04.02.The capacity model tracks available or configured capacity separately at subsystem, Endurance Group, NVM Set, and namespace levels. Values from different levels are not directly interchangeable.
- Endurance Group
- Endurance Group, a group of NVM resources for isolating and reporting endurance-related state.
- NVM Set
- NVM Set, a capacity grouping that associates namespaces with a managed set of NVM resources.
Sources: Base 2.4 §3.8
Source: NVME-BASE-2.4, Rev. 2.4, §3.8, printed pages 125-129, PDF pages 151-155
| Memory or capacity level | Resource provided | Checks before use or comparison |
|---|---|---|
| CMB | Controller-provided working memory | Capability bits decide whether SQs, CQs, lists, or data may reside there |
| PMR | A region with persistence semantics | Enable, ready, error, and address control must be read together |
| Capacity model | Capacity of subsystem/group/set/namespace levels | Fields from different levels must not be subtracted directly |
05 Shutdown, reset, and retained state
05.01.The common lifecycle question is which layer of state remains valid. Normal shutdown coordinates through CC.SHN and CSTS.SHST; resets exist at subsystem, controller, and queue levels; Keep Alive monitors host-controller liveness; firmware activation may require a particular reset. The same temporary inability to process commands does not imply the same recovery.
- SHN
- Shutdown Notification, the CC field through which the host declares a shutdown type.
05.02.Normal shutdown begins when the host sets CC.SHN and the controller reports progress in CSTS.SHST. NVM subsystem shutdown has a wider scope and is not the same as one controller shutdown.
- NVM subsystem
- NVM subsystem, the NVMe system boundary containing controllers, ports, namespaces, and non-volatile storage resources.
Sources: Base 2.4 §3.6.1, 3.6.3
Source: NVME-BASE-2.4, Rev. 2.4, §3.6.1, 3.6.3, printed pages 113-120, PDF pages 139-146
| Shutdown or reset event | Target and purpose | Completion or state-retention evidence |
|---|---|---|
| Normal shutdown | Protected stop with progress reporting | Observe SHN/SHST |
| Controller reset | Controller-scope state | Queue preservation depends on reset type |
| NVM subsystem reset | Wider subsystem scope | May affect multiple controllers |
| Keep Alive timeout | Liveness failure | Must not be equated with media failure |
Where to continue in the specification
06.01.Use the flow above to frame the problem, then open the corresponding sections for fields and full conditions. The Chinese tutorial also explains every in-scope figure with its takeaway, example, and details.
| Concept to explain | Specification sections |
|---|---|
| Controller types, identifiers, and capabilities | Base 2.4 §3.1.1 · Base 2.4 §3.1.3-3.1.3.2 · Base 2.4 §3.1.3 |
| Initialization from configuration to CSTS.RDY | Base 2.4 §3.1.4 · Base 2.4 §3.5.1, 3.5.3-3.5.4 |
| Queue positions and command selection | Base 2.4 §3.3.1 · Base 2.4 §3.4.1-3.4.5 · Base 2.4 §3.1.3 |
| Namespaces, CMB, PMR, and capacity | Base 2.4 §3.1.4 · Base 2.4 §3.8 · Base 2.4 §3.2.2-3.2.4 |
| Shutdown, reset, and retained state | Base 2.4 §3.6.1, 3.6.3 · Base 2.4 §3.7 · Base 2.4 §3.9 · Base 2.4 §3.10-3.11 |
Check your understanding
1. Does a reported controller capability establish that it is ready for I/O?
07.01.Capability describes what is supported; initialization and ready state describe whether operation can begin now. Queue setup, enablement, and readiness checks still precede use under the applicable conditions.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §3.1.4, printed pages 52-54, PDF pages 78-80
Source: NVME-BASE-2.4, Rev. 2.4, §3.5.1, 3.5.3-3.5.4, printed pages 105-113, PDF pages 131-139
2. Must a command submitted earlier in an SQ complete first?
07.02.Submission order, controller work selection, and completion order are distinct. SQ position alone generally cannot establish completion order; dependencies require the synchronization or command mechanisms defined by the specification.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §3.3.1, printed pages 88-91, PDF pages 114-117
Source: NVME-BASE-2.4, Rev. 2.4, §3.4.1-3.4.5, printed pages 101-105, PDF pages 127-131
3. Why is an orderly shutdown not equivalent to a reset?
07.03.Shutdown includes host notification and controller completion status, providing an explicit handoff before power removal. A reset changes controller or subsystem state according to its level. Their triggers, scope, and retained states differ.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §3.6.1, 3.6.3, printed pages 113-120, PDF pages 139-146
Source: NVME-BASE-2.4, Rev. 2.4, §3.7, printed pages 120-125, PDF pages 146-151
4. Why can controller-visible memory regions not all be counted as namespace capacity?
07.04.A namespace provides storage addressed as logical blocks. Regions such as CMB and PMR have their own purposes, access methods, and persistence rules. Being on the same device does not give them the same capacity or data model.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §3.2.2-3.2.4, printed pages 80-85, PDF pages 106-111
Source: NVME-BASE-2.4, Rev. 2.4, §3.8, printed pages 125-129, PDF pages 151-155
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