繁體中文 00.01.A host knows which namespace an I/O targets, but the controller can also benefit from knowing which storage set a submission queue is intended to serve. SQ Associations supplies that hint when the queue is created. This report connects storage membership, queue setup and command routing, explaining when the hint helps and why successful I/O alone does not prove correct routing.SQ AssociationsA queue-creation hint identifying the NVM Set that an SQ is intended to serve.controllerController, the entity that implements the NVMe interface, fetches commands, and reports completions.namespaceA logical storage space selected by NSID.HostThe system running the operating system and...
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NVMe SQ Associations: From Storage Membership to I/O Queue Routing
00.01.A host knows which namespace an I/O targets, but the controller can also benefit from knowing which storage set a submission queue is intended to serve. SQ Associations supplies that hint when the queue is created. This report connects storage membership, queue setup and command routing, explaining when the hint helps and why successful I/O alone does not prove correct routing.
- SQ Associations
- A queue-creation hint identifying the NVM Set that an SQ is intended to serve.
- controller
- Controller, the entity that implements the NVMe interface, fetches commands, and reports completions.
- namespace
- A logical storage space selected by NSID.
- Host
- The system running the operating system and issuing NVMe commands.
- I/O
- Input/Output, the class of data operations performed on a namespace.
- SQ
- Submission Queue; a memory queue in which the host places commands for execution.
The main ideas
Distinguish three relationships
01-01A namespace belongs to a set, an SQ is associated with a set, and completions go to a CQ. Each relationship answers a different question; identifiers are not interchangeable.
- CQ
- Completion Queue; a memory queue in which the controller posts command completions.
Check the hint’s prerequisites
02-01Discover controller support, distinguish mode enablement from support, and consider the set’s current operating window. Capability bits alone provide no fixed application-latency bound.
Connect storage queries to queue creation
03-01Read actual set identifiers and namespace membership, then encode Create I/O SQ. List index, byte position and identifier serve different purposes, as does the count encoding for a 64-entry queue.
- entry
- One list record; an NVM Set Attributes Entry occupies 128 bytes.
- index
- A zero-based entry position within the list.
Check routing for each I/O
04-01Follow command NSID to set to an associated SQ. Compare invalid creation parameters with later queue misuse and their different specified consequences.
- NSID
- Namespace Identifier; identifies the namespace targeted by an I/O command.
00.02.Assumes operating systems, computer organization and basic SSD knowledge. Sets 7/9, SQ3/4/5, CQ2 and namespace identifiers are illustrative; actual support and identifiers come from the device.
00.03.Start with the queue selection for one I/O, establish the overview, then follow queries, fields and results.
Connecting the main ideas
00.04.One example runs throughout: namespaces A/B belong to set 7 and C to set 9. SQ3/SQ4 serve set 7, SQ5 serves set 9, and completions can share CQ2. Follow where each identifier comes from, where it is encoded and how it selects an SQ.
00.05.SQ Associations is an optional hint for Predictable Latency Mode. Support for the hint, correctness of the hint and the mode’s current quality of service are separate questions.
- Predictable Latency Mode
- A mode providing deterministic read/write latency per NVM Set during operating windows subject to specified conditions.
01 Tell the controller which set a queue serves
- NVMSETID
- A 16-bit NVM Set identifier, distinct from SQ identifiers and NSIDs.
- NVM Set
- A logically separate collection of non-volatile memory that may contain multiple namespaces.
- NVM
- Non-Volatile Memory, memory that retains data without power.
01.01.SQ Associations lets a host associate an I/O Submission Queue with an NVM Set at queue creation, providing a hint for improved performance with Predictable Latency Mode. It is optional; Predictable Latency Mode does not depend on using SQ Associations.
Sources: Base 2.4 §8.1.28
Source: NVME-BASE-2.4, Rev. 2.4, §8.1.28, printed pages 732-733, PDF pages 758-759
02 Separate support, mode state and operating windows
| Observation | What it establishes | What it does not establish |
|---|---|---|
| Three CTRATT bits are one | SQA, NVM Sets and PLM are supported | Mode is currently enabled for set 7 |
| Mode enabled for set 7 | Operating-window rules apply to that set | The set must currently be in DTWIN |
| Set 7 is in DTWIN | Deterministic latency under its conditions | Unlimited workload or a bound on all PCIe latency |
| SQ3 associated with set 7 | The controller received the queue hint | Every later I/O is necessarily routed correctly |
- CTRATT
- Controller Attributes; a field of capability bits in Identify Controller.
- DTWIN
- Deterministic Window; the operating window in which a set can provide deterministic read/write latency.
- PCIe
- PCI Express, the transport and device interconnect used by an NVMe memory-based controller.
- PLM
- Predictable Latency Mode; the CTRATT bit reporting mode support.
- SQA
- SQ Associations; the CTRATT bit reporting support for queue-to-set association.
02.01.A controller supporting SQ Associations must advertise SQA, NVM Sets and Predictable Latency Mode in CTRATT. These support bits do not mean that every set has the mode enabled or is currently in a deterministic window.
Sources: Base 2.4 §8.1.28
Source: NVME-BASE-2.4, Rev. 2.4, §8.1.28, printed pages 732-733, PDF pages 758-759
03 Map namespaces to sets before routing commands
| List index | Byte range in the list | NSETID inside the entry | Use at SQ creation |
|---|---|---|---|
| 0 | 128–255 | 7 | CDW12=00000007h |
| 1 | 256–383 | 9 | CDW12=00000009h |
- NSETID
- NVM Set Identifier; the name used for the set identifier in an NVM Set Attributes Entry.
- NUMENT
- Number of Entries; the number of entries actually returned in the list.
- CDW
- CDW (Command Dword): a 32-bit command field. In CDW10, 10 is the field index, not a byte offset.
03.01.The host needs two kinds of information: the NVM Set List identifies accessible sets, while Identify Namespace identifies the set containing a namespace. List position, NVM Set Identifier and NSID are different values.
Sources: Base 2.4 §5.2.14.2.4
Source: NVME-BASE-2.4, Rev. 2.4, §5.2.14.2.4, printed pages 388-389, PDF pages 414-415
04 Select both the set and completion queue when creating an SQ
| Command location | Composition in this example | Encoded value |
|---|---|---|
| CDW10 | Upper 16: 64−1=63; lower 16: QID3 | 003F0003h |
| CDW11 | Upper 16: CQID2; PC=1; QPRIO=0 | 00020001h |
| CDW12 | Lower 16: set 7; upper 16 reserved | 00000007h |
| PRP1 | Allocated contiguous host memory, 4 KiB aligned | 0000000000100000h |
- QPRIO
- Queue Priority; used only by the applicable weighted round-robin arbitration mechanism.
- PRP1
- PRP Entry 1; holds the queue base or PRP List address according to PC.
- PC
- Physically Contiguous; one selects contiguous queue memory, zero a page-list description.
04.01.Create I/O Submission Queue uses CDW12.NVMSETID for the set association and CDW11.CQID for the destination completion queue. NVMSETID=0 or unsupported SQA means no specific set association. With SQA supported, a nonzero identifier absent from the set list must cause Invalid Field in Command.
- CQID
- Completion Queue Identifier; selects the destination CQ for this SQ’s completions.
Sources: Base 2.4 §5.3.2
Source: NVME-BASE-2.4, Rev. 2.4, §5.3.2, printed pages 529-531, PDF pages 555-557
05 Keep each I/O’s set consistent with its SQ association
05.01.To obtain the benefits of SQ Associations, the host must associate each I/O submission queue with an NVM Set and send commands only to queues matching the set containing the command’s NSID. Violating the operating rules may affect Predictable Latency; this section does not define mandatory access-control rejection of mismatched commands.
Sources: Base 2.4 §8.1.28
Source: NVME-BASE-2.4, Rev. 2.4, §8.1.28, printed pages 733, PDF pages 759
A forward route through the specification
R-1Explain the mechanism with the overview and examples, then follow these Base PDF viewer pages in order. On shared pages, start at the specified heading and stop before the next named heading. The Chinese tutorial explains necessary background without repeated reference detours.
| Page order | Start section | Focus and stop heading |
|---|---|---|
| R1 · Base PDF 363–365 | §5.2.14 | Read CNS/CNSSID in Figures 333/334, then only CNS 01h/04h/08h and their relevant footnotes in Figure 336. Skip the other CNS rows. Stop before §5.2.14.1. |
| R2 · Base PDF 370–372 | §5.2.14.2.1 | In Figure 338, locate CTRATT at bytes 99:96 and read only SQA bit 8, PLM bit 5 and NSETS bit 2. Stop after those bits. Stop before §5.2.14.2.2. |
| R3 · Base PDF 414–415 | §5.2.14.2.4 | Start at NVM Set List. Use entries for sets 7/9 to explain the starting ID, NUMENT and entries, separating the 128-byte stride from actual identifiers. Stop before §5.2.14.2.5. |
| R4 · Base PDF 416–419 | §5.2.14.2.8 | Check the response condition for an active NSID, then locate NVMSETID at bytes 11:10 and adjacent ENDGID in Figure 346. Stop after membership fields. Stop before §5.2.14.2.9. |
| R5 · Base PDF 555–557 | §5.3.2 | Connect Figures 575–579 with SQ3, CQ2 and set 7, emphasizing the different roles of CDW12/CDW11 and the result of an invalid set at creation. Stop before §5.3.3. |
| R6 · Base PDF 708–709 | §8.1.21 | Read the mode introduction, Figure 751 and the operating conditions in §8.1.21.1, stopping before Figure 752. Separate window state from mode enablement without expanding full configuration. Stop before §8.1.21.2. |
| R7 · Base PDF 758–759 | §8.1.28 | Start at Submission Queue (SQ) Associations and conclude with the complete primary scope: optional hint, support prerequisites, association at creation and the two host routing rules. Stop before §8.1.29. |
- CNSSID
- CNS Specific Identifier; its meaning depends on the selected CNS value.
- ENDGID
- Endurance Group Identifier; identifies the endurance group containing a set or namespace.
- CNS
- Controller or Namespace Structure; selects the data returned by Identify.
Check your understanding
1. Do all three capability bits being one guarantee the completion time of the next read?
07.01.No. They report support. Check mode enablement for the target set, the current window and operating limits; the quality-of-service description also excludes PCIe connection latency.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §8.1.28, printed pages 732-733, PDF pages 758-759
Source: NVME-BASE-2.4, Rev. 2.4, §8.1.21, printed pages 682-683, PDF pages 708-709
2. Entry 1 contains NSETID=9. Should queue creation encode 1, 256 or 9?
07.02.Encode 9. One is the index, 256 is the entry’s byte offset from the list start, and nine is the set identifier for CDW12.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §5.2.14.2.4, printed pages 388-389, PDF pages 414-415
Source: NVME-BASE-2.4, Rev. 2.4, §5.3.2, printed pages 529-531, PDF pages 555-557
3. NSID21 belongs to set 9, and SQ3/SQ5 share CQ2. Can either SQ be selected?
07.03.Use SQ5, associated with set 9 in this example. Sharing a CQ only shares the completion destination; SQ3 remains associated with set 7.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §8.1.28, printed pages 733, PDF pages 759
Source: NVME-BASE-2.4, Rev. 2.4, §3.3, printed pages 88, PDF pages 114
4. Does NVMSETID=0 create a shared hint for every set?
07.04.No. Create I/O SQ defines zero as no association with a specific set. It does not provide the association required for the routing discipline described here.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §5.3.2, printed pages 529-531, PDF pages 555-557
Source: NVME-BASE-2.4, Rev. 2.4, §8.1.28, printed pages 733, PDF pages 759
5. An I/O for set 9 succeeds on an SQ associated with set 7. Does success prove correct host use?
07.05.No. Misrouting violates the operating rules and may affect predictable latency; §8.1.28 does not require rejection with an error each time. This differs from an unsupported nonzero set identifier at SQ creation, which must cause Invalid Field in Command.
Sources
Source: NVME-BASE-2.4, Rev. 2.4, §8.1.28, printed pages 733, PDF pages 759
Source: NVME-BASE-2.4, Rev. 2.4, §5.3.2, printed pages 529-531, PDF pages 555-557
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