1. Establish the source and scope

These are CC.MPS memory pages, not NAND pages or namespace LBAs.

Check supported and selected MPS; page size is 2^(12+MPS) bytes.

2. Fields, units and worked interpretation

Ordinary PRP1 contains a page base and Dword-aligned offset; special commands can instead define a list pointer.

Calculate P−offset before deciding whether more pages are required.

With page 4096, offset 1024 and length 2048, the 3072-byte remainder suffices and PRP2 is reserved.

3. Conditions that change the interpretation

Create Queue requires page-aligned PRP1 and does not inherit ordinary first-data-page offset freedom.

Verify length with offset and page size; a sub-page transfer can still cross a boundary.

1. Mechanism and scope

This applies to ordinary PRP data layouts, subject to command-specific definitions.

2. Understand it through actions and results

Derive the required pages from MPS, first offset and total length.

3. Avoid a misleading conclusion

A wrong interpretation can turn data into addresses; detection before any transfer is not guaranteed.

Verify the pointed content matches the derived role, not merely a nonzero address.

1. Establish the source and scope

The list covers data not already described by in-command PRPs.

Use page size and eight-byte entries to calculate capacity.

2. Fields, units and worked interpretation

A nonfinal list page uses its last entry as a page-aligned link to the next list page.

Pack only required entries and use a chain only when additional coverage is necessary.

Teaching example: a page-aligned 4 KiB list has 512 slots: 511 data pointers plus a link when nonfinal, or up to 512 data pointers when final. The first PRP List pointer may have a Qword-aligned page offset. At offset 64 bytes, (4096−64)÷8 = 504 slots remain; if another list page is needed, the last slot is its link, leaving up to 503 data-page entries. The next list page starts at its page boundary. Use Figure 93 to determine whether PRP2 is a list pointer, then §4.3.1 and Figures 111–113 for offsets, entries, and links.

3. Conditions that change the interpretation

Remaining transfer length determines whether the final slot is data or linkage.

Retain command lists until completion, but queue lists until successful deletion or reset.

1. Establish the source and scope

Apply selected MPS and pointer role, not an assumed OS page size.

Identify first data, first list pointer, list data entry or chained-list pointer.

2. Fields, units and worked interpretation

Ordinary first data is Dword aligned; the first list pointer is Qword aligned with possible page offset; later data and list pages are page aligned.

Check alignment and remaining capacity of the first list page.

A first list starting at 4080 within a 4 KiB page has two slots, with the last used for linkage if needed.

3. Conditions that change the interpretation

Low-two-bit violations may produce PRP Offset Invalid or must be treated as cleared; nonzero later-page offsets should produce that error.

Permitted controller tolerance does not remove host alignment obligations.

1. Distinguish the failure conditions

Separate format, coverage and actual transfer failures.

Invalid offsets differ from transfer failures; address zero alone does not establish either result.

No unique CQE is defined for every malformed chain or inaccessible address, especially if communication fails.

CQE

Completion Queue Entry

2. Establish the cause from evidence

Check MPS, pointer roles, required pages and accessible memory ranges.

Isolate one change from a valid baseline and inspect the complete required address coverage.

3. Outcome and follow-up checks

A valid accessible layout can succeed, and reserved PRP2 zero is not a missing page.

Preserve SQE, list contents and mapping before host changes obscure evidence.

SQE

Submission Queue Entry

First establish that the command actually uses the pointer.

1. What differs

SGLs apply to supported PCIe I/O commands, not PCIe Admin commands.

Descriptors are 16 bytes; types 0h/2h/3h distinguish data, segment and last segment, whose length describes descriptor bytes.

2. How to choose and verify

Establish SGL support and PSDT data/metadata layout.

One block fits directly in SGL1; multiple blocks use a pointed descriptor array.

Last Segment length 32 means two descriptors, not 32 payload bytes; payload length comes from those entries.

3. Conditions that shape the comparison

Link descriptors must be last in their segment, and a last segment cannot contain another link.

Account descriptor and payload bytes separately.

1. Distinguish the failure conditions

Data and metadata SGL length errors have distinct statuses.

Segment addresses are Qword aligned with nonzero 16-byte-multiple lengths; zero-length data blocks are valid.

Misplaced links require 0/0Eh; links inside a last segment 0/0Dh; unsupported types 0/11h; short data/metadata 0/0Fh or 0/10h.

2. Establish the cause from evidence

Check alignment, longer-length support, descriptor types and requested transfer length.

Traverse boundaries, link position, type/subtype and aggregate data coverage.

3. Outcome and follow-up checks

The SGL must cover the request; LLDTS1 permits excess capacity without enlarging the transfer.

Excess length with LLDTS0 should not cause abort; if it does, the corresponding length status is recommended. Alignment rules retain their may/should strengths.

First establish a concrete structural violation rather than infer one from bad data.

1. Select the target and information

Capabilities remain constrained by transport and command type.

SGLS low bits encode unsupported, unrestricted data-block alignment, or Dword alignment/granularity.

LLDTS, SBBDS, MSDS/MBA and SDT respectively cover excess length, bit buckets, metadata and recommended count.

2. Query sequence and interpretation

Select valid PSDT and supported PCIe types/subtypes; do not import another transport’s offset format.

Dword granularity requires four-byte address/length multiples, not page alignment.

3. Handle missing or inconsistent evidence

Simulated data: a PCIe controller supports Bit Bucket and reports SDT=2. A read destination SGL has two nonzero-length Data Blocks and one nonzero-length Bit Bucket. Under §4.3.2 the SDT count is three, so performance may be reduced; exceeding the recommendation alone does not require command failure. Segment descriptors and zero-length Data Blocks are excluded from this count. Figure 338 defines SDT=0 as no recommended maximum reported. MSDBD limits descriptors in a capsule, not all PCIe memory-list descriptors.

Legal behavior must match capabilities while retaining the Admin SGL prohibition.

First decode individual SGLS fields instead of testing nonzero.

1. What differs

Detection can occur during descriptor validation or memory access.

Preserve layout and completion fields; Error Information PEL means Parameter Error Location, not Persistent Event Log.

2. How to choose and verify

Validate layout/coverage and memory lifetime at the time of access.

Exclude premature buffer reclamation before diagnosing access to a valid address.

Valid pointers and successful transfer do not alone prove the requested media operation succeeded.

3. Conditions that shape the comparison

Data Transfer Error is 0/04h, distinct from pointer-format statuses; not every transfer failure is a host formatting error.

Valid SGL portions may transfer before another descriptor fails; an error CQE does not prove an untouched buffer.

CQE

Completion Queue Entry

1. Preserve the evidence first

Match controller, queue lifetime and SQID/CID; reusable identifiers alone are insufficient.

SQID

Submission Queue Identifier

CID

Command Identifier, unique among outstanding commands in one SQ

Preserve status and auxiliary bits before reading applicable error information.

Error count, command identity, status and parameter location help correlation, including invalid/unspecified location encodings.

2. Work through the possible causes

First preserve the original command/list before retry overwrites them.

Correlate identity/status before byte/bit locations; list-memory errors need not identify a unique SQE bit.

SQE

Submission Queue Entry

3. Connect observations to specification conditions

A matched record connects original fields, violated conditions and returned status.

More 0 does not prohibit an entry, not every error requires one, and DNR0 does not justify reusing a malformed list.

Overwritten or reset-cleared history limits evidence rather than proving validity.

4. Correlate error completions and records

For a CQE, DNR=1 means the identical command is expected to fail if resubmitted to any controller in this subsystem; DNR=0 means it may succeed. Read the complete conditions in this volume

DNR

Do Not Retry, a completion retry indication

A successful CQE does not require a new Error Information entry. Read the complete conditions in this volume