1. Prepare the operation

Each SQ/CQ has its own doorbell; updating one does not update another.

Verify a valid queue, a ready controller, sufficient free slots and the register address derived from CAP.DSTRD.

SQ Tail points to the next insertion slot; CQ Head points to the next completion to consume. Writes contain new pointer values, not increments.

2. Sequence and completion conditions

Make complete SQEs visible using the platform's memory-ordering requirements before updating Tail. Consume valid CQEs before updating Head; batching is allowed.

The controller learns which commands can be fetched and which CQ slots can be reused. Advancing CQ Head does not submit new I/O.

3. Handle unmet conditions

Releasing unconsumed CQEs risks overwrite. Submitting incomplete SQEs violates usage ordering and has no guaranteed single error CQE.

Build a timeline of SQE writes, Tail updates, CQE phase changes and Head updates; they have distinct roles.

SQE

Submission Queue Entry

1. Distinguish the failure conditions

Errors affect the target queue and possibly SQs sharing its CQ. Access to a nonexistent queue differs from an invalid value on an existing queue.

Valid indices lie in 0..size−1; a numerically smaller value may be a valid wrap. Do not assume that rewriting the same value is a harmless no-op: Base 2.4 Figure 153 lists it as a possible cause of Invalid Doorbell Write Value.

For an invalid value on an existing queue with an outstanding Asynchronous Event Request (AER), the controller reports Invalid Doorbell Write Value through that AER. The event information is not a CQE status for the MMIO write. Without an outstanding AER, this rule alone does not establish notification. A write to a nonexistent queue doorbell has undefined behavior.

MMIO

Memory-Mapped I/O, mapped device-register access

2. Establish the cause from evidence

Need size, previous pointer, available/consumed slots and QID mapping. The new value alone is insufficient.

Teaching example: for size=8, Tail 6→1 advances three slots, provided three are free and populated. A 6→6 write cannot announce a full ring and may be an invalid write.

3. Outcome and follow-up checks

A valid movement communicates the correct count. Doorbell readback is vendor-specific and is not a verification method.

Compare old pointer, ring size and available space, not just numeric ordering. Correlate the error event with affected-queue command consumption.

First calculate (new−old+size) modulo size and verify that the resulting advance is legal.

4. Check notifications and log records separately

Base §3.3.1.2 specifies an error event for an invalid doorbell value with an outstanding Asynchronous Event Request. An affected SQ may complete consumed commands but consumes no new ones; the host deletes and recreates the queue.

Follow the Error event’s indicated log for additional information; the MMIO write itself has no More bit. Do not invent mandatory logging for undefined nonexistent-QID accesses.

MMIO

Memory-Mapped I/O, mapped device-register access

1. Establish the source and scope

Offsets are relative to the controller's MMIO base, not a queue's memory address.

PCI BAR0/BAR1 locate the NVMe register space; CAP.DSTRD provides adjacent-doorbell stride.

2. Fields, units and worked interpretation

stride=4×2^DSTRD; SQy offset=1000h+2y×stride; CQy offset=1000h+(2y+1)×stride. Each doorbell itself remains 32 bits.

Obtain the mapped base, calculate stride, select the SQ/CQ expression for QID, then access with a legal MMIO width.

DSTRD=2 and QID=3 give SQ offset 1060h and CQ offset 1070h. Add the controller base for full addresses.

3. Conditions that change the interpretation

Address calculation has no status. A wrong address can select another valid queue or an undefined location; the controller cannot infer host intent.

Match results against created QIDs and the mapped BAR range. DSTRD is an exponent, not a byte count or a direct QID multiplier.

BAR

Base Address Register

1. Establish the queue lifetime

Use each queue after successful creation and retire it after successful deletion or controller reset.

Check host queue-lifetime records, CC.EN and CSTS.RDY; doorbell readback cannot establish queue existence.

SQyTDBL/CQyHDBL announce pointers for valid queues. Admin Q0's environment comes from AQA/ASQ/ACQ and initialization.

Create successfully, use, stop submissions, successfully delete, then stop all use. Reused QIDs after reset still require reconstruction.

2. No fixed response for a nonexistent queue

PCIe §3.1.2 defines writes to nonexistent SQ/CQ doorbells as undefined. RDY=0 violates submission prerequisites. No guaranteed Invalid Queue Identifier or AER follows.

Use Create/Delete completion times to establish the valid interval and check doorbell timestamps against it.

1. Prepare the operation

The host advances SQ Tail and CQ Head; the controller maintains SQ Head and CQ Tail.

Use the actual N=QSIZE+1 slots, not CAP.MQES as every queue's size.

Advance with (index+1) modulo N. Tail is the next insertion position, Head the next consumption position; equality means empty.

2. Sequence and completion conditions

Wrap N−1 to zero while tracking the real count. Do not overfill the SQ or release unconsumed CQ entries.

With N=8, CQ Head 7→2 consumes slots 7, 0 and 1: three entries, not a backward movement of five.

3. Handle unmet conditions

Valid wrap is not an error. Writing N as an index is out of range; invalid-pointer handling follows Question 23.

Validate modulo relationships among Head, Tail and size. A decreasing doorbell value alone is not a violation.

1. Prepare the operation

Phase belongs to the CQ ring lifetime; it is neither CID success/failure nor an SQ pointer.

CID

Command Identifier, unique among outstanding commands in one SQ

This is a basic PCIe CQE mechanism, not an optional feature. Initialize every slot's phase to zero before creation and initially expect one.

CQE DW3 bit 16 is P. Each new posting in a slot inverts that slot's previous phase.

2. Sequence and completion conditions

CID

Command Identifier, unique among outstanding commands in one SQ

3. Handle unmet conditions

A phase mismatch means no new completion at that position, not an error status. Do not decode stale CID/SC as a new result.

Exercise at least one wrap and compare Head, expected P and actual P. Reinitialize after queue recreation rather than inheriting the old phase.

1. Mechanism and scope

It affects the CQ and associated SQs. Processing must continue for SQs not associated with that full CQ.

Full means (Tail+1) modulo N = Head, leaving one slot unused. Tail is controller-internal, not directly readable by the host.

2. Understand it through actions and results

Inspect actual CQ size, Head updates and pending completions, not Number of Queues.

The host validates phases, processes results and advances Head. The controller shall not post another completion to this CQ until a slot is available.

The controller may stop processing further associated SQ entries. This does not require all consumed commands either to stop instantly or to continue unconditionally.

3. Avoid a misleading conclusion

CQ Full is a capacity state, not a required error status. Overwriting unacknowledged entries to make room violates correctness.

If only its associated SQs stall, inspect consumption first. If independent SQs stop because of this full CQ, check the requirement to continue their processing.

1. Prepare the operation

Released slots serve completions from associated SQs; queue allocations and namespace capabilities do not change.

Verify a live queue and no independent stop condition such as reset, CFS or Processing Paused.

The host writes the new CQ Head, allowing the controller to reuse released slots with correct phases for subsequent completions.

2. Sequence and completion conditions

Consume CQEs, update Head, allow slots to become available, then post waiting completions and continue affected work under normal scheduling and other constraints.

Released slots are reusable without recreation. There is no universal fixed latency from a Head update to the next CQE.

3. Handle unmet conditions

Correct release has no special success CQE. An invalid Head remains a doorbell-usage issue, not a Create Queue error.

Verify legal reuse of released slots and compare progress on associated and independent SQs.

1. Establish the source and scope

Matching includes controller, SQ lifetime, SQID and CID. Controller/lifetime are host context, not additional CQE fields.

SQID

Submission Queue Identifier

Use the creation-time SQ-to-CQ map and outstanding table, not Identify for per-command locations.

2. Fields, units and worked interpretation

SQID identifies the SQ and CID its command. SQHD reports consumption progress, not the original slot of that command.

SQID

Submission Queue Identifier

Validate phase first, match SQID/CID, process status/data, update that SQ's head information, then release the CQ slot.

SQ1/CID 9 and SQ2/CID 9 are matched correctly even if they complete in reverse order.

3. Conditions that change the interpretation

Reusing an outstanding CID in one SQ may return Command ID Conflict (0/03h). The conflict-search extent is implementation-specific; host uniqueness obligations remain.

Check that SQID is associated with this CQ and CID belongs to its current queue lifetime.